[PATCH 0/2] powerpc: i2c-mpc: make I2C bus speed configurable

[Wolfgang Grandegger]

Following (most of) Grant's suggestions to my RFC:

http://ozlabs.org/pipermail/linuxppc-dev/2009-March/069820.html

this new patch series now uses:

- the I2c node property "fsl,preserve-clocking" to overtake the
  clock settings from the boot loader. The first patch provides this
  feature and can be applied *without* delay. This rest will take
  more time and discussion, I'm afraid  :-( .

- the OF match table to define the I2C clock properties, especially
  the source clock pre-scaler:

  static const struct of_device_id mpc_i2c_of_match[] = {
	{.compatible = "fsl,mpc5200b-i2c",
	 .data = (void *)FSL_I2C_DEV_CLOCK_5200, },
	{.compatible = "fsl,mpc5200-i2c",
	 .data = (void *)FSL_I2C_DEV_CLOCK_5200, },
	{.compatible = "fsl,mpc8313-i2c",
	 .data = (void *)FSL_I2C_DEV_SEPARATE_DFSRR, },
	{.compatible = "fsl,mpc8543-i2c",
	 .data = (void *)(FSL_I2C_DEV_SEPARATE_DFSRR |
			  FSL_I2C_DEV_CLOCK_DIV2), },
	{.compatible = "fsl,mpc8544-i2c",
	 .data = (void *)(FSL_I2C_DEV_SEPARATE_DFSRR |
			  FSL_I2C_DEV_CLOCK_DIV23), },
	/* Backward compatibility */
	{.compatible = "fsl-i2c", },
	{},
  };

  The "data" field defines the relevant I2C flags.

- arch-specific tables and functions to get the proper Freqency
  Divider Register (fdr). I added them to sysdev/fsl_soc.c for
  the MPC8xxx and to platforms/52xx/mpc52xx_common.c for the
  MPC52xx. This also solves the problem with arch-specific
  functions, e.g. for getting the bus frequency.

- dev_dbg() and dev_info() to profit from a more descriptive output.

Hope this solution is OK now?

Thanks,

Wolfgang.