[Cbe-oss-dev] [PATCH 3:6] spufs: remove class_0_dsisr from spu exception handling
Luke Browning
lukebr at linux.vnet.ibm.com
Tue May 13 00:37:11 EST 2008
Remove class_0_dsisr from spu exception handling.
According to the CBEA, the dsisr is not updated for class 0
exceptions. The value of the register is unarchitected for
class 0 exceptions. spu_stopped() is testing the dsisr that
was passed to it from the class 0 exception handler and the
test that it is making is for a class 1 exception!
This patch cleans up the interrupt handler and erroneous
tests in spu_stopped. It also removes the fields from the
csa since it is not needed to process class 0 events.
Signed-off-by: Luke Browning <lukebrowning at us.ibm.com>
---
Index: spufs/arch/powerpc/platforms/cell/spu_base.c
===================================================================
--- spufs.orig/arch/powerpc/platforms/cell/spu_base.c
+++ spufs/arch/powerpc/platforms/cell/spu_base.c
@@ -324,14 +324,12 @@ spu_irq_class_0(int irq, void *data)
stat = spu_int_stat_get(spu, 0) & mask;
spu->class_0_pending |= stat;
- spu->class_0_dsisr = spu_mfc_dsisr_get(spu);
spu->class_0_dar = spu_mfc_dar_get(spu);
spin_unlock(&spu->register_lock);
spu->stop_callback(spu, 0);
spu->class_0_pending = 0;
- spu->class_0_dsisr = 0;
spu->class_0_dar = 0;
spu_int_stat_clear(spu, 0, stat);
@@ -373,9 +371,6 @@ spu_irq_class_1(int irq, void *data)
if (stat & CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR)
;
- spu->class_1_dsisr = 0;
- spu->class_1_dar = 0;
-
return stat ? IRQ_HANDLED : IRQ_NONE;
}
Index: spufs/arch/powerpc/platforms/cell/spufs/run.c
===================================================================
--- spufs.orig/arch/powerpc/platforms/cell/spufs/run.c
+++ spufs/arch/powerpc/platforms/cell/spufs/run.c
@@ -27,7 +27,6 @@ void spufs_stop_callback(struct spu *spu
switch(irq) {
case 0 :
ctx->csa.class_0_pending = spu->class_0_pending;
- ctx->csa.class_0_dsisr = spu->class_0_dsisr;
ctx->csa.class_0_dar = spu->class_0_dar;
break;
case 1 :
@@ -35,11 +34,19 @@ void spufs_stop_callback(struct spu *spu
ctx->csa.class_1_dar = spu->class_1_dar;
break;
case 2 :
+ /*
+ * No arguments need to be passed. The delivery of the
+ * event is synchronous wrt the controlling thread which
+ * reads the spu status register to determine the nature
+ * of the event, stop-n-signal, ...
+ */
break;
}
- /* ensure that the exception status has hit memory before a
- * thread waiting on the context's stop queue is woken */
+ /*
+ * Ensure that the exception status has hit memory before a
+ * thread waiting on the context's stop queue is woken
+ */
smp_wmb();
wake_up_all(&ctx->stop_wq);
@@ -66,10 +73,6 @@ int spu_stopped(struct spu_context *ctx,
if (test_bit(SPU_SCHED_NOTIFY_ACTIVE, &ctx->sched_flags))
return 1;
- dsisr = ctx->csa.class_0_dsisr;
- if (dsisr & (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED))
- return 1;
-
dsisr = ctx->csa.class_1_dsisr;
if (dsisr & (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED))
return 1;
Index: spufs/arch/powerpc/xmon/xmon.c
===================================================================
--- spufs.orig/arch/powerpc/xmon/xmon.c
+++ spufs/arch/powerpc/xmon/xmon.c
@@ -2844,7 +2844,6 @@ static void dump_spu_fields(struct spu *
DUMP_FIELD(spu, "0x%lx", flags);
DUMP_FIELD(spu, "%d", class_0_pending);
DUMP_FIELD(spu, "0x%lx", class_0_dar);
- DUMP_FIELD(spu, "0x%lx", class_0_dsisr);
DUMP_FIELD(spu, "0x%lx", class_1_dar);
DUMP_FIELD(spu, "0x%lx", class_1_dsisr);
DUMP_FIELD(spu, "0x%lx", irqs[0]);
Index: spufs/include/asm-powerpc/spu.h
===================================================================
--- spufs.orig/include/asm-powerpc/spu.h
+++ spufs/include/asm-powerpc/spu.h
@@ -131,7 +131,6 @@ struct spu {
u64 flags;
u64 class_0_pending;
u64 class_0_dar;
- u64 class_0_dsisr;
u64 class_1_dar;
u64 class_1_dsisr;
size_t ls_size;
Index: spufs/include/asm-powerpc/spu_csa.h
===================================================================
--- spufs.orig/include/asm-powerpc/spu_csa.h
+++ spufs/include/asm-powerpc/spu_csa.h
@@ -254,7 +254,7 @@ struct spu_state {
u64 spu_chnldata_RW[32];
u32 spu_mailbox_data[4];
u32 pu_mailbox_data[1];
- u64 class_0_dar, class_0_dsisr, class_0_pending;
+ u64 class_0_dar, class_0_pending;
u64 class_1_dar, class_1_dsisr;
unsigned long suspend_time;
spinlock_t register_lock;
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