[Cbe-oss-dev] new product zego announced

[Arnd Bergmann]

On Monday 18 August 2008, Akira Tsukamoto wrote:

> On Sat, 16 Aug 2008 15:07:27 +0200, Arnd Bergmann <arnd at arndb.de> mentioned: 
> > How do you use the DDR2 and PCIe memory? Do you plan to use axonram
> > for that or something different? I assume both of them will not
> > be cache-coherent, so you can only efficiently use them for SPU code,
> > but not through CI accesses from the PPU, right?
> 
> The South bridge chip is the same with Toshiba Celleb and QS20 and do 
> not have axonram.

Well, most of the axonram driver is not specific to the axon bridge,
so it should be easy to adapt for the SCC memory controller. In the
simplest case, you would not handle ECC errors in there at all and
just use the block device.

The interesting aspect of axonram is that it supports the azfs
file system, which provides a nice abstraction for using memory
from an SPU program.

	Arnd <><