[Cbe-oss-dev] [RFC/PATCH] adding support for direct MBX interrupt on Axon based platform.

[Benjamin Herrenschmidt]

> +static void c3po_mask(unsigned int irq)
> +{
> +}
> +
> +static void c3po_unmask(unsigned int irq)
> +{
> +}
> +
> +static void c3po_eoi(unsigned int irq)
> +{
> +}
> +
> +static void c3po_ack(unsigned int irq)
> +{
> +}
> +
> +static struct irq_chip c3po_chip = {
> +	.typename = " AXON-C3PO",
> +	.mask = c3po_mask,
> +	.unmask = c3po_unmask,
> +	.ack = c3po_ack,
> +	.eoi = c3po_eoi,
> +};

I think you need none of that.

> +static void c3po_irq_cascade(unsigned int irq, struct irq_desc *desc)
> +{
> +	int hw_int = (int)desc->handler_data;
> +	unsigned int virq = irq_find_mapping(NULL, hw_int);
> +
> +	if (virq != NO_IRQ) {
> +		generic_handle_irq(virq);
> +	}
> +
> +	desc->chip->eoi(irq);
> +}

Why that cascade chip etc... ?

If you use a different class, you get a unique IRQ number straight off
the IIC. Thus you can just register an IIC interrupt !

  .../...

Basically, -all- you need is

 - Add a quirk to change the IRC class (or fix your OF)
 - Sythetize a HW irq number off the IIC (or fix our OF :-)
 - Map and request the above.

The IRQ number would be defined from the constants in interrupts.h, that
is the node in bit 8, the class 0x10, and the source (0x0 or 0xb) in the
low 4 bits.

If you put it in the device-tree, then the "interrupts" property shall
contain NN XX CC UU, where NN is the node, EXT isn't used in your case,
CC is the class and UU the unit. For example, for node 0 class 1 unit 0:
0x00000100. In which case you can just use irq_of_parse_and_map() on the
mbx node which contains that property to obtain a virq you can request.

Cheers,
Ben.