[Cbe-oss-dev] [PATCH] axonram: 1st version

[Arnd Bergmann]

On Thursday 15 February 2007 19:17, Jean-Christophe Dubois wrote:
> The DDR2 is not cache coherent in the Axon.

That's exactly the point Christoph was making. The phram driver
maps the memory cacheable by default, so we need to change the
driver to use cache-inhibited mode on axon ram.

> So one thing we would like to do is to define some kind of "partition table" 
> and store it in NVRAM. This way the "partition" will be persistent over 
> reset/reboot even on the CAB. Remember that on the CAB there is no permanent 
> storage (disk or even NFS server) and by default we run an embedded type 
> distribution from a Ramdisk (why would you need a full distro for an 
> accelerator).
> 
> If the "partition table" is in the NVRAM then the host can also read it (or 
> write it even if I think we should not allow this) to know what part of the 
> DDR is reserved for the Cell and what part it can use for its own purpose.

Having the partition table in nvram sounds wacky, so I wouldn't like
to see that in a generic driver. However, with the phram driver, it
is not that unusual, since a lot of embedded systems already have
MTD with wacky partitioning schemes, and one more probably won't hurt
much.
 
> In the CAB scenario the DDR can be used by as a kind of buffer to stage the 
> data to be processed by the Cell/SPUs. Maybe this can also be of some value 
> in the blade case to dedicate part of the DDR for "swap" and part of it as a 
> working buffer for SPUs or other things.
> 
> Maybe the "partitioning" could even merge 2 memory banks into one (with a hole 
> in the middle).

Right, that makes sense to do on the partitioning level. We could perhaps
have a driver that reads the partition table from some nvram method if available
and otherwise falls back to using the memory banks as partitions.

	Arnd <><