[Cbe-oss-dev] [PATCH]:Add PM signal groups registers.

[takaki.azuma]

Hello,

I'm working at Toshiba on porting perfmon2 to the Toshiba Cell platform.

This is a patch to access the registers for the PM signal pass-through and
for the PPE signal groups. I added the register definition to structures
included in cbe_regs.h. In addition, I added the cbe_ppe_priv_regs structure
to cbe_regs.h, because it is necessary to access several registers of the
PPE privilage 1 mmio area. cbe_fill_regs_map() maps PPE privilage 1 area by
the same procedure as other mmio areas. (This doesn't correspond to SMP).

Thanks,

-- Takaki Azuma

Signed-off-by: Takaki Azuma <takaki.azuma at dme.toshiba.co.jp>
Signed-off-by: Takayuki Uchikawa <takayuki.uchikawa at toshiba.co.jp>

Index: powerpc/arch/powerpc/platforms/cell/cbe_regs.h
===================================================================
--- powerpc.git/arch/powerpc/platforms/cell/cbe_regs.h
+++ powerpc/arch/powerpc/platforms/cell/cbe_regs.h
@@ -118,7 +118,12 @@ struct cbe_pmd_regs {
 #define CBE_PMD_FIR_MODE_M8		0x00800
 	u64	fir_enable_mask;				/* 0x0c20 */
 
-	u8	pad_0x0c28_0x0ca8 [0x0ca8 - 0x0c28];		/* 0x0c28 */
+	u8	pad_0x0c28_0x0c98 [0x0c98 - 0x0c28];		/* 0x0c28 */
+
+	u64	on_ramp_trace;					/* 0x0c98 */
+
+	u8	pad_0x0ca0_0x0ca8 [0x0ca8 - 0x0ca0];		/* 0x0ca0 */
+
 	u64	ras_esc_0;					/* 0x0ca8 */
 	u8	pad_0x0cb0_0x1000 [0x1000 - 0x0cb0];		/* 0x0cb0 */
 };
@@ -210,7 +215,15 @@ struct cbe_iic_regs {
 	u64	ioc_syserr_enable;				/* 0x0520 */
 	u64	ioc_fir;					/* 0x0528 */
 
-	u8	pad_0x0530_0x1000[0x1000 - 0x0530];		/* 0x0530 */
+	u8	pad_0x0530_0x0600[0x0600 - 0x0530];		/* 0x0530 */
+
+	u64	ioc_dtb_cfg0;					/* 0x0600 */
+
+	u8	pad_0x0608_0x0618[0x0618 - 0x0608];		/* 0x0608 */
+
+	u64	ioc_dtb_cfg3;					/* 0x0618 */
+
+	u8	pad_0x061c_0x1000[0x1000 - 0x061c];		/* 0x061c */
 };
 
 extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
@@ -218,7 +231,11 @@ extern struct cbe_iic_regs __iomem *cbe_
 
 
 struct cbe_mic_tm_regs {
-	u8	pad_0x0000_0x0040[0x0040 - 0x0000];		/* 0x0000 */
+	u8	pad_0x0000_0x0010[0x0010 - 0x0000];		/* 0x0000 */
+
+	u64	MBL_debug;					/* 0x0010 */
+
+	u8	pad_0x0018_0x0040[0x0040 - 0x0018];		/* 0x0018 */
 
 	u64	mic_ctl_cnfg2;					/* 0x0040 */
 #define CBE_MIC_ENABLE_AUX_TRC		0x8000000000000000LL
@@ -226,8 +243,7 @@ struct cbe_mic_tm_regs {
 #define CBE_MIC_DISABLE_AUX_TRC_WRAP	0x0100000000000000LL
 #define CBE_MIC_ENABLE_AUX_TRC_INT	0x0080000000000000LL
 
-	u64	pad_0x0048;					/* 0x0048 */
-
+	u64	mic_ctl_debug2;					/* 0x0048 */
 	u64	mic_aux_trc_base;				/* 0x0050 */
 	u64	mic_aux_trc_max_addr;				/* 0x0058 */
 	u64	mic_aux_trc_cur_addr;				/* 0x0060 */
@@ -239,8 +255,7 @@ struct cbe_mic_tm_regs {
 	u64	mic_ctl_cnfg_0;					/* 0x0080 */
 #define CBE_MIC_DISABLE_PWR_SAV_0	0x8000000000000000LL
 
-	u64	pad_0x0088;					/* 0x0088 */
-
+	u64	mic_ctl_debug_0;				/* 0x0088 */
 	u64	slow_fast_timer_0;				/* 0x0090 */
 	u64	slow_next_timer_0;				/* 0x0098 */
 
@@ -248,17 +263,65 @@ struct cbe_mic_tm_regs {
 
 	u64	mic_ctl_cnfg_1;					/* 0x01c0 */
 #define CBE_MIC_DISABLE_PWR_SAV_1	0x8000000000000000LL
-	u64	pad_0x01c8;					/* 0x01c8 */
 
+	u64	mic_ctl_debug_1;				/* 0x01c8 */
 	u64	slow_fast_timer_1;				/* 0x01d0 */
 	u64	slow_next_timer_1;				/* 0x01d8 */
 
-	u8	pad_0x01e0_0x1000[0x1000 - 0x01e0];		/* 0x01e0 */
+	u8	pad_0x01e0_0x0220[0x0220 - 0x01e0];		/* 0x01e0 */
+
+	u64	mic_df_debug_yrac_0;				/* 0x0220 */
+	u64	mic_df_debug_yrac_1;				/* 0x0228 */
+
+	u8	pad_0x0230_0x0238[0x0238 - 0x0230];		/* 0x0230 */
+
+	u64	mic_fir_debug;					/* 0x0238 */
+
+	u8	pad_0x0240_0x0ff0[0x0ff0 - 0x0240];		/* 0x0240 */	
+
+	u64	tkm_pmcr;					/* 0x0ff0 */
+
+	u8	pad_0x0ff8_0x1000[0x1000 - 0x0ff8];		/* 0x0ff8 */
 };
 
 extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
 extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
 
+/*
+ *
+ *  PPE Privileged MMIO Registers definition. (offset 0x500000 - 0x500fff)
+ *
+ */
+struct cbe_ppe_priv_regs {
+	u8	pad_0x0000_0x0838[0x0838 - 0x0000];		/* 0x0000 */
+
+	u64	L2_perfmon1;					/* 0x0838 */
+
+	u8	pad_0x0840_0x0858[0x0858 - 0x0840];		/* 0x0840 */
+
+	u64	L2_debug1;					/* 0x0858 */
+
+	u8	pad_0x0860_0x0958[0x0958 - 0x0860];		/* 0x0860 */
+
+	u64	ciu_dr1;					/* 0x0958 */
+	u64	ciu_dr2;					/* 0x0960 */
+
+	u8	pad_0x0968_0x0a50[0x0a50 - 0x0968];		/* 0x0968 */
+
+	u64	ncu_dr1;					/* 0x0a58 */
+	u64	ncu_dr2;					/* 0x0a60 */
+
+	u8	pad_0x0a68_0x0b58[0x0b58 - 0x0a68];		/* 0x0a68 */
+
+	u64	biu_dbgperfmon;					/* 0x0b58 */
+
+	u8	pad_0x0b60_0x1000[0x1000 - 0x0b60];		/* 0x0b60 */
+};
+
+#define BP_BASE_OFFSET_PPE_MMIO_REGS	0x500000ul
+
+extern struct cbe_ppe_priv_regs __iomem * cbe_get_cpu_ppe_priv_regs(int cpu);
+
 /* some utility functions to deal with SMT */
 extern u32 cbe_get_hw_thread_id(int cpu);
 extern u32 cbe_cpu_to_node(int cpu);
Index: powerpc/arch/powerpc/platforms/cell/cbe_regs.c
===================================================================
--- powerpc.git/arch/powerpc/platforms/cell/cbe_regs.c
+++ powerpc/arch/powerpc/platforms/cell/cbe_regs.c
@@ -34,6 +34,7 @@ static struct cbe_regs_map
 	struct cbe_iic_regs __iomem *iic_regs;
 	struct cbe_mic_tm_regs __iomem *mic_tm_regs;
 	struct cbe_pmd_shadow_regs pmd_shadow_regs;
+	struct cbe_ppe_priv_regs __iomem * ppe_priv_regs;
 } cbe_regs_maps[MAX_CBE];
 static int cbe_regs_map_count;
 
@@ -146,6 +147,14 @@ struct cbe_mic_tm_regs __iomem *cbe_get_
 }
 EXPORT_SYMBOL_GPL(cbe_get_cpu_mic_tm_regs);
 
+struct cbe_ppe_priv_regs __iomem * cbe_get_cpu_ppe_priv_regs(int cpu)
+{
+	struct cbe_regs_map * map = cbe_thread_map[cpu].regs;
+	if (map == NULL)
+		return NULL;
+	return map->ppe_priv_regs;
+}
+
 u32 cbe_get_hw_thread_id(int cpu)
 {
 	return cbe_thread_map[cpu].thread_id;
@@ -228,6 +237,10 @@ void __init cbe_fill_regs_map(struct cbe
 		prop = of_get_property(cpu, "mic-tm", NULL);
 		if (prop != NULL)
 			map->mic_tm_regs = ioremap(prop->address, prop->len);
+
+		prop = of_get_property(cpu, "bp-base", NULL);
+		if (prop != NULL)
+			map->ppe_priv_regs = ioremap(prop->address + BP_BASE_OFFSET_PPE_MMIO_REGS, sizeof(struct
cbe_ppe_priv_regs));
 	}
 }