[Cbe-oss-dev] [PATCH] spufs: wrap mfc sdr access

[Geoff Levand]

The PPE's SPRN_SDR1 and the SPE's MFC SDR are hypervisor resources, and
are not accessible from a logical partition.  This change adds an
access wrapper.

When running on bare H/W, the spufs needs to only set the SPE's MFC SDR
to the value of the PPE's SPRN_SDR1 once at SPE initialization, so this
change renames mfc_sdr_set() to mfc_sdr_setup() and moves the
access of SPRN_SDR1 into the mmio wrapper.  It also removes the now
unneeded member mfc_sdr_RW from struct spu_priv1_collapsed.


Signed-off-by: Masato Noguchi <Masato.Noguchi at jp.sony.com>
Signed-off-by: Geoff Levand <geoffrey.levand at am.sony.com>

--

Index: a/arch/powerpc/platforms/cell/spu_base.c
===================================================================
--- a.orig/arch/powerpc/platforms/cell/spu_base.c	2006-07-25 16:07:13.000000000 -0700
+++ a/arch/powerpc/platforms/cell/spu_base.c	2006-07-25 16:07:14.000000000 -0700
@@ -743,7 +743,7 @@

 	spin_lock_init(&spu->register_lock);

-	spu_mfc_sdr_set(spu, mfspr(SPRN_SDR1));
+	spu_mfc_sdr_setup(spu);
 	spu_mfc_sr1_set(spu, 0x33);
 	spu_smm_pgsz_set(spu, 0x2);

Index: a/arch/powerpc/platforms/cell/spu_priv1_mmio.c
===================================================================
--- a.orig/arch/powerpc/platforms/cell/spu_priv1_mmio.c	2006-07-25 16:07:13.000000000 -0700
+++ a/arch/powerpc/platforms/cell/spu_priv1_mmio.c	2006-07-25 16:07:14.000000000 -0700
@@ -84,9 +84,9 @@
 	out_be64(&spu->priv1->mfc_dsisr_RW, dsisr);
 }

-static void mfc_sdr_set(struct spu *spu, u64 sdr)
+static void mfc_sdr_setup(struct spu *spu)
 {
-	out_be64(&spu->priv1->mfc_sdr_RW, sdr);
+	out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1));
 }

 static void mfc_sr1_set(struct spu *spu, u64 sr1)
@@ -155,7 +155,7 @@
 	.mfc_dar_get = mfc_dar_get,
 	.mfc_dsisr_get = mfc_dsisr_get,
 	.mfc_dsisr_set = mfc_dsisr_set,
-	.mfc_sdr_set = mfc_sdr_set,
+	.mfc_sdr_setup = mfc_sdr_setup,
 	.mfc_sr1_set = mfc_sr1_set,
 	.mfc_sr1_get = mfc_sr1_get,
 	.mfc_tclass_id_set = mfc_tclass_id_set,
Index: a/arch/powerpc/platforms/cell/spufs/switch.c
===================================================================
--- a.orig/arch/powerpc/platforms/cell/spufs/switch.c	2006-07-25 16:07:13.000000000 -0700
+++ a/arch/powerpc/platforms/cell/spufs/switch.c	2006-07-25 16:07:14.000000000 -0700
@@ -2165,9 +2165,6 @@
 	    MFC_STATE1_PROBLEM_STATE_MASK |
 	    MFC_STATE1_RELOCATE_MASK | MFC_STATE1_BUS_TLBIE_MASK;

-	/* Set storage description.  */
-	csa->priv1.mfc_sdr_RW = mfspr(SPRN_SDR1);
-
 	/* Enable OS-specific set of interrupts. */
 	csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
 	    CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR |
Index: a/include/asm-powerpc/spu_csa.h
===================================================================
--- a.orig/include/asm-powerpc/spu_csa.h	2006-07-25 16:07:11.000000000 -0700
+++ a/include/asm-powerpc/spu_csa.h	2006-07-25 16:07:14.000000000 -0700
@@ -151,7 +151,6 @@
 	u64 mfc_fir_chkstp_enable_RW;
 	u64 smf_sbi_signal_sel;
 	u64 smf_ato_signal_sel;
-	u64 mfc_sdr_RW;
 	u64 tlb_index_hint_RO;
 	u64 tlb_index_W;
 	u64 tlb_vpn_RW;
Index: a/include/asm-powerpc/spu_priv1.h
===================================================================
--- a.orig/include/asm-powerpc/spu_priv1.h	2006-07-25 16:07:13.000000000 -0700
+++ a/include/asm-powerpc/spu_priv1.h	2006-07-25 16:15:05.000000000 -0700
@@ -37,7 +37,7 @@
 	u64 (*mfc_dar_get) (struct spu *spu);
 	u64 (*mfc_dsisr_get) (struct spu *spu);
 	void (*mfc_dsisr_set) (struct spu *spu, u64 dsisr);
-	void (*mfc_sdr_set) (struct spu *spu, u64 sdr);
+	void (*mfc_sdr_setup) (struct spu *spu);
 	void (*mfc_sr1_set) (struct spu *spu, u64 sr1);
 	u64 (*mfc_sr1_get) (struct spu *spu);
 	void (*mfc_tclass_id_set) (struct spu *spu, u64 tclass_id);
@@ -113,9 +113,9 @@
 }

 static inline void
-spu_mfc_sdr_set (struct spu *spu, u64 sdr)
+spu_mfc_sdr_setup (struct spu *spu)
 {
-	spu_priv1_ops->mfc_sdr_set(spu, sdr);
+	spu_priv1_ops->mfc_sdr_setup(spu);
 }

 static inline void