[Cbe-oss-dev] [RFC 4/9] AXON - Ethernet over PCI-E driver

[Benjamin Herrenschmidt]

> One model that you could use is to have a statically allocated buffer
> for addresses of incoming data on each side. In pseudocode:

I'm not 100% sure but your example seems to be overlooking some ordering
issues.

The ideal solution (almost no barriers needed) is something around the
lines of what TG3 does.

The rx and tx path are of course completely separate. Then, you have the
descriptor array, and a pair of separate shared memory areas per ring. a
pair because you really want to separate things written by the host from
things written by the cell.

When transfering in direction A -> B, the emitter (A) checks for room by
checking the ring tail in the message area for (B -> A) for room (it
knows the ring head, as it's the sole manipulator for it, it's in (A ->
B) message area.

It then writes packets, updates descriptors, and then (with proper
wmb()'s to make sure things happen in order), update the ring head.

The receiver checks the ring head, compares it to the ring tail and
consume data when appropriate.

That works fine for lock-less and almost barrier-less NAPI poll(). In
addition, you can add a mecanism to trigger interrupts (based on
threshold, or a "I want an IRQ" bit somewhere or whatever), in which
case the ISR needs to perform an MMIO read on the host end to flush
store buffers, and then schedules a NAPI poll.

Ben.