<div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div>Hi everyone,<br><br></div>We are currently developing a RDIMM with CPUs inside the DRAM chips. This DIMM does not have ECC support and then I would like to disable ECC check and correct, ie I want to set the bit 0 of the register RECR (page 210 of POWER9_Registers_vol3_version1.2_pub.pdf).  I successfully do that in Hostboot, during the DRAM initialization.<br><br>My problem is that it seems that this register is "reset" during the transition from Hostboot to Skiboot: does that seem plausible to you ?</div><br></div><div>The platform I'm working on is a<span style="font-size:11pt;font-family:Arial;color:rgb(0,0,0);background-color:transparent;font-weight:400;font-style:normal;font-variant:normal;text-decoration:none;vertical-align:baseline;white-space:pre-wrap"> <font size="2">TL2MB1 (<a href="https://wiki.raptorcs.com/wiki/Talos_II">https://wiki.raptorcs.com/wiki/Talos_II</a>).<br>The code I'm based on is a custom hostboot/skiboot developed by RaptorCS team:<br>- hostboot: <a href="https://scm.raptorcs.com/scm/git/talos-hostboot">https://scm.raptorcs.com/scm/git/talos-hostboot</a> 884b60b16009061ab84db88f918902a8c8098a4b<br></font></span></div><div><span style="font-size:11pt;font-family:Arial;color:rgb(0,0,0);background-color:transparent;font-weight:400;font-style:normal;font-variant:normal;text-decoration:none;vertical-align:baseline;white-space:pre-wrap"><font size="2">- skiboot: <a href="https://scm.raptorcs.com/scm/git/talos-skiboot">https://scm.raptorcs.com/scm/git/talos-skiboot</a> bc106a09b0ab298ec71b3ef8337fb5f820a7c454<br></font></span></div><div dir="ltr"><div dir="ltr"><br></div><div>Below is the trace I get of this transition:<br></div><div><b><br></b> 51.69046|ISTEP 21. 2 - host_verify_hdat^M                                       <br> 51.70166|ISTEP 21. 3 - host_start_payload<b><br># This is the value I'm interested in, as you can see, bit 63 is set. </b><br></div><div dir="ltr"><b></b><div><div> 51.72614|FAPI|call_host_start_payload.C: UPMEM: 0x7010a0a value is : <b>0x8890a23810800000</b>^M<br> 51.72616|FAPI|call_host_start_payload.C: UPMEM:<b> PIR: 0x80d</b>^M                    <br>^M                                                                               <br>[   51.501846781,5] OPAL bc106a09-upmem-dirty-c19e811 starting...^M              <br>[   51.501851186,7] initial console log level: memory 7, driver 5^M              <br>[   51.501853342,6] CPU: P9 generation processor (max 4 threads/core)^M          <br>[   51.501855276,7] CPU: Boot CPU PIR is 0x081c PVR is 0x004e1202^M              <br>[   51.501857947,7] OPAL table: 0x30101230 .. 0x301017e0, branch table: 0x30002000^M<br>[   51.501860995,7] Assigning physical memory map table for nimbus^M             <br>[   51.501864003,7] Parsing HDAT...^M                                            <br>[   51.501865320,5] SPIRA-S found.^M                                             <br>[   51.501867765,6] BMC #0: HW version 3, SW version 2, chip DD1.0^M             <br>[   51.501895710,4] SENSORS: Duplicate sensor ID : 0^M                           <br>[   51.501897519,4] SENSORS: Duplicate sensor ID : 0^M                           <br>[   51.501906010,4] SENSORS: Duplicate sensor ID : 0^M                           <br>[   51.501911808,4] SENSORS: Duplicate sensor ID : 0^M                           <br>[   51.501942832,6] SP Family is ibm,ast2500,openbmc^M                           <br>[   51.501949550,7] LPC: IOPATH chip id = 0^M                                    <br>[   51.501950989,7] LPC: FW BAR       = f0000000^M                               <br>[   51.501952683,7] LPC: MEM BAR      = e0000000^M                               <br>[   51.501954472,7] LPC: IO BAR       = d0010000^M                               <br>[   51.501956092,7] LPC: Internal BAR = c0012000^M                               <br>[   51.501968744,7] LPC UART: base addr = 3f8 (3f8) size = 1 clk = 1843200, baud = 115200^M<br>[   51.501971651,7] LPC: BT [0, 0] sms_int: 0, bmc_int: 0^M                      <br>[   51.502871058,5] UART: Using UART at 0x60300d00103f8^M                        <br>[   51.504754984,3] UPMEM: __xscom_read: gcid, read address gcid:0x0 0x0x603fc00780078^M<br>[   51.504860126,3] UPMEM: __xscom_read: gcid, read address gcid:0x0 0x0x603fc000c0010^M<br>[   51.504930258,5] P9 DD2.21 detected^M                                         <br>[   51.504955724,5] CHIP: Chip ID 0000 type: P9N DD2.2^M                         <br>[   51.504992069,3] UPMEM: __xscom_read: gcid, read address gcid:0x0 0x0x603fc38085050^M<br></div><div><b># I re-read the same address: as you can see, the PIR seems to indicate that I'm on<br></b></div><div><b># the same socket but the value I read is not the same I read from Hostboot.<br></b></div><div>[   51.505061382,3] UPMEM: xscom_init: recr value gcid = 0, <b>pir = 81c, @0x7010a0a = 0xa10603810800000</b>^M<br>[   51.505149206,3] UPMEM: __xscom_read: gcid, read address gcid:0x8 0x0x623fc00780078^M<br>[   51.505211582,3] UPMEM: __xscom_read: gcid, read address gcid:0x8 0x0x623fc000c0010^M<br>[   51.505264687,5] P9 DD2.21 detected^M                                         <br>[   51.505286188,5] CHIP: Chip ID 0008 type: P9N DD2.2^M                         <br>[   51.505321741,3] UPMEM: __xscom_read: gcid, read address gcid:0x8 0x0x623fc38085050^M<br></div><div><b># I tried the other XSCOM device (?)</b><br></div><div>[   51.505396556,3] UPMEM: xscom_init: recr value gcid = 8,<b> pir = 81c, @0x7010a0a = 0xa10603810800000</b>^M<br>[   51.505475821,3] UPMEM: xscom_init^M                <br><br></div><div>I can provide provide any needed information :)<br><br></div><div>Thanks in advance,<br><br></div><div>Alexandre Ghiti<br></div><div>                       <br></div></div></div></div></div></div></div></div></div></div></div></div></div>