<html><head><meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body dir="auto"><div>Do you have code elsewhere to set the register in the SLW?  You need to update the SLW as well. Though, I think the RPR is only cleared on winkle and not sleep. <br><br><div>Patrick Williams</div><div><span style="font-size: 13pt;">Sent from my iPhone</span></div></div><div><br>On Jun 18, 2015, at 12:30 AM, Benjamin Herrenschmidt <<a href="mailto:benh@kernel.crashing.org">benh@kernel.crashing.org</a>> wrote:<br><br></div><blockquote type="cite"><div><span>The value was provided by Dave Larson and is what pHyp uses</span><br><span></span><br><span>Signed-off-by: Benjamin Herrenschmidt <<a href="mailto:benh@kernel.crashing.org">benh@kernel.crashing.org</a>></span><br><span>---</span><br><span>diff --git a/asm/head.S b/asm/head.S</span><br><span>index fd6e3fb..6963188 100644</span><br><span>--- a/asm/head.S</span><br><span>+++ b/asm/head.S</span><br><span>@@ -707,6 +707,9 @@ init_shared_sprs:</span><br><span>     sync</span><br><span>     mtspr    SPR_HMEER,%r3</span><br><span>     isync</span><br><span>+    /* RPR (per-LPAR but let's treat it as replicated for now) */</span><br><span>+    LOAD_IMM64(%r3,0x00000103070F1F3F)</span><br><span>+    mtspr    SPR_RPR,%r3</span><br><span> 9:    blr</span><br><span></span><br><span> .global init_replicated_sprs</span><br><span>diff --git a/include/processor.h b/include/processor.h</span><br><span>index c9e9d0e..e8f0c3c 100644</span><br><span>--- a/include/processor.h</span><br><span>+++ b/include/processor.h</span><br><span>@@ -52,6 +52,7 @@</span><br><span> #define SPR_SRR0    0x01a    /* RW: Exception save/restore reg 0 */</span><br><span> #define SPR_SRR1    0x01b    /* RW: Exception save/restore reg 1 */</span><br><span> #define SPR_CFAR    0x01c    /* RW: Come From Address Register */</span><br><span>+#define SPR_RPR        0x0ba   /* RW: Relative Priority Register */</span><br><span> #define SPR_TBRL    0x10c    /* RO: Timebase low */</span><br><span> #define SPR_TBRU    0x10d    /* RO: Timebase high */</span><br><span> #define SPR_SPRC    0x114    /* RW: Access to uArch SPRs (ex SCOMC) */</span><br><span></span><br><span></span><br><span>_______________________________________________</span><br><span>Skiboot mailing list</span><br><span><a href="mailto:Skiboot@lists.ozlabs.org">Skiboot@lists.ozlabs.org</a></span><br><span><a href="https://lists.ozlabs.org/listinfo/skiboot">https://lists.ozlabs.org/listinfo/skiboot</a></span><br></div></blockquote></body></html>