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<small>Missed to attach the dtc output in description, please
ignore..<br>
Resending.<br>
<br>
Neelesh.<br>
</small><br>
<div class="moz-cite-prefix">On 05/21/2015 11:26 AM, Neelesh Gupta
wrote:<br>
</div>
<blockquote
cite="mid:20150521055432.21981.6790.stgit@localhost.localdomain"
type="cite">
<pre wrap="">Fetch the memory bus frequency present in PCIA area and
add this information to the memory node.
Signed-off-by: Neelesh Gupta <a class="moz-txt-link-rfc2396E" href="mailto:neelegup@linux.vnet.ibm.com"><neelegup@linux.vnet.ibm.com></a>
Reviewed-by: Vasant Hegde <a class="moz-txt-link-rfc2396E" href="mailto:hegdevasant@linux.vnet.ibm.com"><hegdevasant@linux.vnet.ibm.com></a>
---
v1 -> v2
- Document the new property 'ibm,memory-bus-frequency' under DIMM
VPD node.
doc/device-tree/vpd.txt | 2 ++
hdata/memory.c | 54 +++++++++++++++++++++++++++++++++++++++++++++--
2 files changed, 54 insertions(+), 2 deletions(-)
diff --git a/doc/device-tree/vpd.txt b/doc/device-tree/vpd.txt
index 949ee0b..4e0c8dd 100644
--- a/doc/device-tree/vpd.txt
+++ b/doc/device-tree/vpd.txt
@@ -15,6 +15,8 @@ part-number : Part number
serial-number : Serial number
ibm,chip-id : Processor Id
size : DIMM size (applicable for DIMM VPD only)
+ibm,memory-bus-frequency: DIMM frequency (applicable for DIMM VPD only),
+ provided as part of the HDAT structure.
The VPD tree in the device tree depicts the hierarchial structure of the
FRUs having parent-child relationship.
diff --git a/hdata/memory.c b/hdata/memory.c
index 019e5fe..352dc71 100644
--- a/hdata/memory.c
+++ b/hdata/memory.c
@@ -159,7 +159,7 @@ static bool add_address_range(struct dt_node *root,
return true;
}
-static void add_chip_id_to_ram_area(const struct HDIF_common_hdr *msarea,
+static u32 add_chip_id_to_ram_area(const struct HDIF_common_hdr *msarea,
struct dt_node *ram_area)
{
const struct HDIF_array_hdr *arr;
@@ -172,6 +172,53 @@ static void add_chip_id_to_ram_area(const struct HDIF_common_hdr *msarea,
arange = (void *)arr + be32_to_cpu(arr->offset);
chip_id = pcid_to_chip_id(be32_to_cpu(arange->chip));
dt_add_property_cells(ram_area, "ibm,chip-id", chip_id);
+
+ return chip_id;
+}
+
+static void add_bus_freq_to_ram_area(struct dt_node *ram_node, u32 chip_id)
+{
+ const struct sppcia_cpu_timebase *timebase;
+ bool got_pcia = false;
+ const void *pcia;
+ u64 freq;
+ u32 size;
+
+ pcia = get_hdif(&spira.ntuples.pcia, SPPCIA_HDIF_SIG);
+ if (!pcia) {
+ prlog(PR_WARNING, "HDAT: Failed to add memory bus frequency "
+ "as PCIA does not exist\n");
+ return;
+ }
+
+ for_each_pcia(pcia) {
+ const struct sppcia_core_unique *id;
+
+ id = HDIF_get_idata(pcia, SPPCIA_IDATA_CORE_UNIQUE, &size);
+ if (!id || size < sizeof(*id)) {
+ prlog(PR_WARNING, "HDAT: Bad id size %u @ %p\n", size, id);
+ return;
+ }
+
+ if (chip_id == pcid_to_chip_id(be32_to_cpu(id->proc_chip_id))) {
+ got_pcia = true;
+ break;
+ }
+ }
+
+ if (got_pcia == false)
+ return;
+
+ timebase = HDIF_get_idata(pcia, SPPCIA_IDATA_TIMEBASE, &size);
+ if (!timebase || size < sizeof(*timebase)) {
+ prlog(PR_ERR, "HDAT: Bad timebase size %u @ %p\n", size,
+ timebase);
+ return;
+ }
+
+ freq = ((u64)be32_to_cpu(timebase->memory_bus_frequency)) *1000000ul;
+ dt_add_property_cells(ram_node, "ibm,memory-bus-frequency", hi32(freq),
+ lo32(freq));
}
static void add_size_to_ram_area(struct dt_node *ram_node,
@@ -207,6 +254,7 @@ static void vpd_add_ram_area(const struct HDIF_common_hdr *msarea)
const struct HDIF_child_ptr *ramptr;
const struct HDIF_ram_area_id *ram_id;
struct dt_node *ram_node;
+ u32 chip_id;
ramptr = HDIF_child_arr(msarea, 0);
if (!CHECK_SPPTR(ramptr)) {
@@ -227,7 +275,9 @@ static void vpd_add_ram_area(const struct HDIF_common_hdr *msarea)
(be16_to_cpu(ram_id->flags) & RAM_AREA_FUNCTIONAL)) {
ram_node = dt_add_vpd_node(ramarea, 0, 1);
if (ram_node) {
- add_chip_id_to_ram_area(msarea, ram_node);
+ chip_id = add_chip_id_to_ram_area(msarea,
+ ram_node);
+ add_bus_freq_to_ram_area(ram_node, chip_id);
add_size_to_ram_area(ram_node, ramarea, 1);
}
}
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</pre>
</blockquote>
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