[Skiboot] (no subject)

[Nicholas Piggin]

On Fri, 01 Dec 2017 14:51:56 -0600
Benjamin Herrenschmidt <benh at kernel.crashing.org> wrote:

> On Fri, 2017-12-01 at 01:52 +1000, Nicholas Piggin wrote:
> > Firstly, Linux should set up MMU registers like PIDR properly in
> > its per-CPU mmu initialisation at boot, patch for that should not
> > be controversial.  
> 
> So I was wondering how we got things into the PWC since we are 
> in real mode when we do the flush, but the above explains it.
> 
> We come up with a stale PIDR and turn the MMU on. We only
> execute/load/store from Q3 but prefetch/speculation can hit Q0 and thus
> get crap into the PWC.
> 
> So I think setting PIDR to 0 is the main fix. Cleaning up the rest also
> makes sense of course.
> 
> Or am I missing something else still ?

Yes that's what happens. After realizing this, the bug no longer requires
translations to be cached in real mode (does the architecture guarantee
that?)

I think LPID is safer to be zeroed as well because in theory we might
get speculative access into quadrant 0/1.

Thanks,
Nick