<div class="socmaildefaultfont" dir="ltr" style="font-family:Arial, Helvetica, sans-serif;font-size:10pt" ><div dir="ltr" >What does "resets" mean? I'm guessing that means you checkstopped? Using the BMC to read the error registers via FSI could help track down the issue. My guess would be an invalid address of some kind.</div>
<div dir="ltr" > </div>
<div dir="ltr" >From your notes I see that you attempted cache-inhibited loads, that is the correct approach. I've never used QEMU so I can't tell you why it failed, but that is what we use when running in real mode. (When running in user-space in normal Hostboot we map cache-inhibited pages into the page table.)</div>
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<div dir="ltr" ><tt>> tried to set MSB, to avoid HRMOR translation.</tt></div>
<div dir="ltr" >You don't set this bit for cache-inhibited addresses, only real mainstore. That might be your issue.</div>
<div dir="ltr" > </div>
<div dir="ltr" >The other weird thing I see in your notes is that your ldcix test is using 623FC00000000 instead of 603FC00000000. Why?</div>
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<div dir="ltr" >I don't see any mention of the HMER, that's how errors are handled (if you don't crash).</div>
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<div dir="ltr" >In your doc you mention fsiscom.C, that is a completely different method. You can't use that to talk to the primary processor itself, you would use that to talk to a secondary processor before the SMP bus is up.</div>
<div dir="ltr" ><br>--<br>Dan Crowell<br>Senior Software Engineer - Power Systems Enablement Firmware<br>IBM Rochester: t/l 553-2987<br>dcrowell@us.ibm.com</div>
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<blockquote data-history-content-modified="1" data-history-expanded="1" dir="ltr" style="border-left:solid #aaaaaa 2px; margin-left:5px; padding-left:5px; direction:ltr; margin-right:0px" >----- Original message -----<br>From: Igor Bagnucki <igor.bagnucki@3mdeb.com><br>Sent by: "OpenPower-Firmware" <openpower-firmware-bounces+dcrowell=us.ibm.com@lists.ozlabs.org><br>To: Christian Geddes <crgeddes@us.ibm.com><br>Cc: openpower-firmware@lists.ozlabs.org, Krystian Hebel <krystian.hebel@3mdeb.com>, Maciej Pijanowski <maciej.pijanowski@3mdeb.com><br>Subject: [EXTERNAL] Re: [OpenPower-Firmware] Questions about SCOM access<br>Date: Thu, Jan 7, 2021 8:45 AM<br> <br><!-- BaNnErBlUrFlE-HeAdEr-start --> <!-- BaNnErBlUrFlE-HeAdEr-end --> <!--Notes ACF
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<p><tt>Thank you for your advice,</tt><br><br><tt>I have followed your suggestion about using base address 0x000603FC00000000.</tt><br><tt>I have also done few other tests and tried to set MSB, to avoid HRMOR translation.</tt><br><tt>It was also discovered during the research, that the register address must be shifted left by 3.</tt><br><tt>The results of the research are gathered in this document: </tt><tt><a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_3mdeb_openpower-2Dcoreboot-2Ddocs_blob_scom-5Faccess_devnotes_scom-5Faccess.md&d=DwMDaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=mCj3CQvqek9g0fdziO-GEHyU1m9T3SAh0ZPd5s_AGpo&m=3UfRiFwAkGZrt9bI3Yd2DYMVw9wX7-eicMpZKn5d4j4&s=Fsmt7fLbmgdykuolICAcCAJ4zqX4BK8enhUauceUA2M&e=" target="_blank" >https://github.com/3mdeb/openpower-coreboot-docs/blob/scom_access/devnotes/scom_access.md</a></tt><br><br><tt>The puzzling thing is that I managed to read SCOM on QEMU, but it's still failing on real HW.</tt><br><br><tt>I'm not sure if it was clear from previous message, but I'm working without any previous initialization from hostboot.</tt><br><tt>Just pure coreboot, started directly by HBBL.</tt><br><br><tt>Do you have any idea, what can be causing HW to fail while reading SCOM?</tt><br><br><tt>--</tt><br><tt>Igor Bagnucki</tt><br><tt>Junior Embedded Firmware Developer</tt><br><tt><a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__3mdeb.com&d=DwMDaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=mCj3CQvqek9g0fdziO-GEHyU1m9T3SAh0ZPd5s_AGpo&m=3UfRiFwAkGZrt9bI3Yd2DYMVw9wX7-eicMpZKn5d4j4&s=uUIq9IMLgXsN1nwsOViXuGOWU-QKCtV6Y_E_RH4bybs&e=" target="_blank" >https://3mdeb.com</a> | @3mdeb_com</tt></p>
<div>On 10.12.2020 22:31, Christian Geddes wrote:</div>
<blockquote cite="mid:OFD532C151.F8596D65-ON0025863A.00761478-0025863A.00763840@notes.na.collabserv.com" type="cite" ><!--Notes ACF
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<div dir="ltr" style="font-family:Arial, Helvetica, sans-serif;font-size:10pt" ><div dir="ltr" ><div><span style="font-family:Courier New,Courier,monospace;" >Hey Igor,</span></div>
<div> </div>
<div><span style="font-family:Courier New,Courier,monospace;" >So as you have probably figure out by now, SCOM registers are 64 bit HW regs<br>IBM puts in all of its its chips. I am not an expert on the subject but I will<br>share how some things work as I understand it.</span></div>
<div><br><span style="font-family:Courier New,Courier,monospace;" >Hostboot configures the hardware using plenty of SCOM registers. How can<br>I access these registers?<br>For example, if I would like to access register PU_OCB_OCI_OCCHBR_SCOM<br>which has the SCOM address of 0x6C08F, how would I access this register?</span></div>
<div> </div>
<div><span style="font-family:Courier New,Courier,monospace;" >There are a few different methods to access SCOM registers depending on what<br>device its on and what point of the boot you are in.</span></div>
<div><span style="font-family:Courier New,Courier,monospace;" >The easiest way to access a scom register is from the primary processor over<br>something we call xscom. XSCOM essentially boils down to accessing an MMIO<br>address offset by the xscom bar passed to us by the SBE via some struct.<br>The default value for group0's XSCOM base addr is 0x000603FC00000000 which<br>is a pretty safe bet if you are having a hard time finding the bootloader<br>structure. Now this base address can change if the SBE sets it to something<br>else, or we end up in some memory swapping scenario, and its going to be<br>different when talking to secondary processors.</span></div>
<div> </div>
<div><span style="font-family:Courier New,Courier,monospace;" >Hostboot takes that XSCOM_BAR and gets a virtual address for it and adds it to<br>(scom address / sizeof(int64)) to get the address we do the memcpy on.</span></div>
<div> </div>
<div><span style="font-family:Courier New,Courier,monospace;" >See xscomDoOp, getTargetVirtualAddress in src/usr/xscom/xscom.C for more info.</span></div>
<div> </div>
<div><br><span style="font-family:Courier New,Courier,monospace;" >Knowing the initial values of the SCOM registers would be very helpful.<br>Are there any documents describing in what state are the registers on<br>power-on?</span></div>
<div> </div>
<div><span style="font-family:Courier New,Courier,monospace;" >The hardware writes most of these registers to 0 at power on (aside from a few<br>inverts), then the SBE comes along and SCANs in a bunch of inital settings.<br>SCAN is another HW access method for the same data in a different address space<br>which is used for writing large amounts of HW settings very quickly. During<br>hostboot many of these registers are set by the FAPI2 hardware procedures<br>you see in /hostboot/src/import/chips/p9/procedures/hwp/initfiles/. If you<br>look at those init files you can see most of the registers are set based on<br>the chip EC level and MRW attributes. Hostboot also sets some registers along<br>the way.</span></div>
<div><br><span style="font-family:Courier New,Courier,monospace;" >I understand that before accessing registers the SCOM controller has to<br>be initialized. Is there some kind of documentation where information<br>about this can be found?</span></div>
<div> </div>
<div><span style="font-family:Courier New,Courier,monospace;" >The SBE should setup the xscom bar for its processor. You will not be able to<br>access SCOMs to the secondary processor until the fabric is initialized<br>between the processors.</span></div>
<div><br><span style="font-family:Courier New,Courier,monospace;" >I hope some of this information helps.</span></div>
<div><br><span style="font-family:Courier New,Courier,monospace;" >Regards,<br>Christian Geddes</span></div></div>
<div dir="ltr" > </div>
<blockquote dir="ltr" style="border-left:solid #aaaaaa 2px; margin-left:5px; padding-left:5px; direction:ltr; margin-right:0px" >----- Original message -----<br>From: Igor Bagnucki <a href="mailto:igor.bagnucki@3mdeb.com" target="_blank" ><igor.bagnucki@3mdeb.com></a><br>Sent by: "OpenPower-Firmware" <a href="mailto:openpower-firmware-bounces+crgeddes=us.ibm.com@lists.ozlabs.org" target="_blank" ><openpower-firmware-bounces+crgeddes=us.ibm.com@lists.ozlabs.org></a><br>To: <a href="mailto:openpower-firmware@lists.ozlabs.org" target="_blank" >openpower-firmware@lists.ozlabs.org</a><br>Cc: <a href="mailto:piotr.krol@3mdeb.commaciej.pijanowski@3mdeb.comkrystian.hebel" target="_blank" >"piotr.krol@3mdeb.com maciej.pijanowski@3mdeb.com krystian.hebel"</a>@3mdeb.com<br>Subject: [EXTERNAL] [OpenPower-Firmware] Questions about SCOM access<br>Date: Thu, Dec 10, 2020 9:33 AM<br>
<div><font size="2" face="Default Monospace,Courier New,Courier,monospace" >Hello,<br><br>I'm doing some initial work at 3mdeb for Insurgo, to bring Power9<br>(specifically Talos II) support into coreboot and I have some questions<br>about SCOM that I can't find an answer for. Reading through documents<br>POWER9_Registers_vol1/2/3, I have found only general information about<br>SCOM controller. I have also tried to find information in the hostboot<br>source code, but the code is quite complicated to understand.<br><br>Hostboot configures the hardware using plenty of SCOM registers. How can<br>I access these registers?<br>For example, if I would like to access register PU_OCB_OCI_OCCHBR_SCOM<br>which has the SCOM address of 0x6C08F, how would I access this register?<br><br>Knowing the initial values of the SCOM registers would be very helpful.<br>Are there any documents describing in what state are the registers on<br>power-on?<br><br>I understand that before accessing registers the SCOM controller has to<br>be initialized. Is there some kind of documentation where information<br>about this can be found?<br><br>--<br>Igor Bagnucki<br>Junior Embedded Firmware Developer<br><a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__3mdeb.com&d=DwMDaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=mCj3CQvqek9g0fdziO-GEHyU1m9T3SAh0ZPd5s_AGpo&m=3UfRiFwAkGZrt9bI3Yd2DYMVw9wX7-eicMpZKn5d4j4&s=uUIq9IMLgXsN1nwsOViXuGOWU-QKCtV6Y_E_RH4bybs&e=" moz-do-not-send="true" target="_blank" >https://3mdeb.com</a> | @3mdeb_com<br><br>_______________________________________________<br>OpenPower-Firmware mailing list<br><a href="mailto:OpenPower-Firmware@lists.ozlabs.org" target="_blank" >OpenPower-Firmware@lists.ozlabs.org</a><br><a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__lists.ozlabs.org_listinfo_openpower-2Dfirmware&d=DwMDaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=mCj3CQvqek9g0fdziO-GEHyU1m9T3SAh0ZPd5s_AGpo&m=3UfRiFwAkGZrt9bI3Yd2DYMVw9wX7-eicMpZKn5d4j4&s=OnXfIp4CYc6ouvaaPjFQb1oLv3a_d-b9e1ZjguLYvBs&e=" moz-do-not-send="true" target="_blank" >https://lists.ozlabs.org/listinfo/openpower-firmware</a> </font><br> </div></blockquote>
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<div><font size="2" face="Default Monospace,Courier New,Courier,monospace" >_______________________________________________<br>OpenPower-Firmware mailing list<br>OpenPower-Firmware@lists.ozlabs.org<br><a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__lists.ozlabs.org_listinfo_openpower-2Dfirmware&d=DwICAg&c=jf_iaSHvJObTbx-siA1ZOg&r=mCj3CQvqek9g0fdziO-GEHyU1m9T3SAh0ZPd5s_AGpo&m=3UfRiFwAkGZrt9bI3Yd2DYMVw9wX7-eicMpZKn5d4j4&s=OnXfIp4CYc6ouvaaPjFQb1oLv3a_d-b9e1ZjguLYvBs&e=" target="_blank" >https://urldefense.proofpoint.com/v2/url?u=https-3A__lists.ozlabs.org_listinfo_openpower-2Dfirmware&d=DwICAg&c=jf_iaSHvJObTbx-siA1ZOg&r=mCj3CQvqek9g0fdziO-GEHyU1m9T3SAh0ZPd5s_AGpo&m=3UfRiFwAkGZrt9bI3Yd2DYMVw9wX7-eicMpZKn5d4j4&s=OnXfIp4CYc6ouvaaPjFQb1oLv3a_d-b9e1ZjguLYvBs&e=</a> </font></div></blockquote>
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