<html><body><p><font size="2">If we move the map, everything moves, including the xscom base addresses. The xscom BAR is setup by the SBE, it isn't changed dynamically with host code once it is established.</font><br><font size="2"><br>--<br>Dan Crowell<br>Senior Software Engineer - Power Systems Enablement Firmware<br>IBM Rochester: t/l 553-2987<br>dcrowell@us.ibm.com</font><br><br><img width="16" height="16" src="cid:1__=09BB0C91DFEBB0788f9e8a93df938690918c09B@" border="0" alt="Inactive hide details for "Marty E. Plummer" ---10/15/2020 09:52:51 AM---On Sun, Oct 11, 2020 at 01:24:05AM +0000, Daniel M Cro"><font size="2" color="#424282">"Marty E. Plummer" ---10/15/2020 09:52:51 AM---On Sun, Oct 11, 2020 at 01:24:05AM +0000, Daniel M Crowell wrote: >> On Fri, Oct 09, 2020 at 01:44:3</font><br><br><font size="2" color="#5F5F5F">From: </font><font size="2">"Marty E. Plummer" <hanetzer@startmail.com></font><br><font size="2" color="#5F5F5F">To: </font><font size="2">Daniel M Crowell <dcrowell@us.ibm.com></font><br><font size="2" color="#5F5F5F">Cc: </font><font size="2">openpower-firmware@lists.ozlabs.org</font><br><font size="2" color="#5F5F5F">Date: </font><font size="2">10/15/2020 09:52 AM</font><br><font size="2" color="#5F5F5F">Subject: </font><font size="2">[EXTERNAL] Re: [OpenPower-Firmware] LPC Address space questions</font><br><hr width="100%" size="2" align="left" noshade style="color:#8091A5; "><br><br><br><tt><font size="2">On Sun, Oct 11, 2020 at 01:24:05AM +0000, Daniel M Crowell wrote:<br>>> On Fri, Oct 09, 2020 at 01:44:34AM +0000, Daniel M Crowell wrote:<br>>>>> What would a situation 'no functional memory behind proc0' look<br>>>>> like in practice? No dram plugged into the proc0 sockets, or busted<br>>>>> dram?<br>>>> Yes, either case could cause it. Either nothing is installed or we find errors and<br>>>> deconfigure/gard what is installed.<br>>> So, for example's sake (not aware of too many different kinds of p9<br>>> systems tbh) lets use the Raptor Computing BlackBird as the device in<br>>> question. One cpu socket, two dram sockets. Assuming 'normal operation',<br>>> this lpc address space will end up always at the location mentioned<br>>> earlier, and it only gets complex on multi-cpu systems?<br>> Correct, this only comes into play on multi-socket systems.<br>Ok, and one more question in this area. Looking at skiboot's hw/xscom.c,<br>its all pretty much big endian mmio accesses, but if it were determined<br>that the address had to be moved (for lack of ram/bad ram/etc), would<br>that movement be achieved via mmio writes to the address we've<br>determined to be unsuitable? Same for the xscom base address, I guess.<br><br></font></tt><br><br><BR>
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