<div class="socmaildefaultfont" dir="ltr" style="font-family:Arial, Helvetica, sans-serif;font-size:10pt" ><div dir="ltr" >Yeah. This was done using remote gdb support in pdbg. We did this using fsp variant of sbe chipops. SBE chipop code for this went in pdbg repo <<span style="text-decoration: underline" ><a href="https://github.rtp.raleigh.ibm.com/shakeebbk-in/pdbg-sbe/commits/master" >https://github.rtp.raleigh.ibm.com/shakeebbk-in/pdbg-sbe/commits/master</a></span>>. It is internal repo as at that time pdbg was not part of openbmc. If you want to access code, Alistair should be able to help in that.</div>
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<div dir="ltr" >Regards</div>
<div dir="ltr" >Sachin</div>
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<blockquote data-history-content-modified="1" dir="ltr" style="border-left:solid #aaaaaa 2px; margin-left:5px; padding-left:5px; direction:ltr; margin-right:0px" >----- Original message -----<br>From: Dean Sanner/Rochester/IBM<br>To: openpower-firmware@lists.ozlabs.org, hanetzer@startmail.com, Raja Das1/India/IBM@IBMIN, Sachin Gupta24/India/IBM@IBMIN, Amit J Tendolkar/India/IBM@IBMIN<br>Cc:<br>Subject: Re: A few questions about early hostboot<br>Date: Wed, Sep 4, 2019 5:49 PM<br> <br><tt><font face="" size="3" >Hi Marty,</font></tt><br><br><tt><font face="" size="3" >> I have a few additional questions about early hostboot on the power9<br>> platform.<br>><br>> I know pdbg has a gdbserver which currently only works on p8 and linux<br>> kernel (though I may be misinterpreting the latter half). I assume the<br>> lack of power9 support is just some missing code for now, but I wonder<br>> about only supporting the linux kernel. Is there some deep-seated reason<br>> one could not use gbdserver on hostboot itself? It could be very useful<br>> for early debugging.</font></tt><br><br><tt><font face="" size="3" >Stewart is correct -- there is just a different way of accessing the memory</font></tt><br><tt><font face="" size="3" >(getmempba versus getmemproc). I know that the IBM's SBE team had a </font></tt><br><tt><font face="" size="3" >prototype of gdbg working against hostboot a while back. I've copied</font></tt><br><tt><font face="" size="3" >them on this email to see if it is still viable (there were some issues</font></tt><br><tt><font face="" size="3" >with the virtual pages for the extended image, but if you are only </font></tt><br><tt><font face="" size="3" >using it for early debug -- might not be an issue).</font></tt><br><br><tt><font face="" size="3" >> <br>> Power9 processors are able to operate in both BE and LE mode, and I am<br>> having a bit of issue following this idea. Is there some register one<br>> sets to switch mode I'm missing, or does the processor just 'know' that<br>> 0xdeadbeef and 0xefbeadde are the same? Forgive me if this is a bad<br>> example but hopefully it gets my point across. In addition, is there any<br>> reason that hostboot couldn't be ran in either big or little endian<br>> (after endian specific code is fixed, obviously)?</font></tt><br><br><tt><font face="" size="3" >There is nothing that prevents Hostboot from running LE mode -- just </font></tt><br><tt><font face="" size="3" >the amount of work to port it :)</font></tt><br><br><tt><font face="" size="3" >MSR bit 63 controls the LE/BE mode (where 0b0 is BE, 0b1 is LE). If</font></tt><br><tt><font face="" size="3" >you want to trampoline early in HB to switch you can setup the srr0/1</font></tt><br><tt><font face="" size="3" >and then rfid to make it take effect. You could hook it into the </font></tt><br><tt><font face="" size="3" >following code from </font></tt><a href="https://github.com/open-power/hostboot/blob/master/src/kernel/start.S" target="_blank" ><tt><font face="" size="3" >https://github.com/open-power/hostboot/blob/master/src/kernel/start.S</font></tt></a><br><tt><font face="" size="3" >(note that this part would need to be BE, all code after _start_postmsr</font></tt><br><tt><font face="" size="3" >would need to be LE)</font></tt><br><br><tt><font face="" size="3" >.global _start</font></tt><br><tt><font face="" size="3" >_start:</font></tt><br><tt><font face="" size="3" > ;// Set thread priority high.</font></tt><br><tt><font face="" size="3" > or 2,2,2</font></tt><br><br><tt><font face="" size="3" > ;// Clear MSR[TA] (bit 1)</font></tt><br><tt><font face="" size="3" > mfmsr r2</font></tt><br><tt><font face="" size="3" > rldicl r2,r2,1,1 ;// Clear bit 1 - result [1-63,0]</font></tt><br><tt><font face="" size="3" > rotrdi r2,r2,1 ;// Rotate right 1 - result [0,63]</font></tt><br><tt><font face="" size="3" > ;// Set up SRR0 / SRR1 to enable new MSR.</font></tt><br><tt><font face="" size="3" > mtsrr1 r2</font></tt><br><tt><font face="" size="3" > li r2, _start_postmsr@l</font></tt><br><tt><font face="" size="3" > mtsrr0 r2</font></tt><br><tt><font face="" size="3" > lis r9,49 ;// Want to default the NAP value</font></tt><br><tt><font face="" size="3" > ori r9,r9,1 ;// Value is 0x0000000000310001</font></tt><br><tt><font face="" size="3" > mtspr 855,r9 ;// set actual PSSCR</font></tt><br><tt><font face="" size="3" > rfid</font></tt><br><br><br><tt><font face="" size="3" >Or you can write the MSR in the SBE code where it manipulates </font></tt><br><tt><font face="" size="3" >the starting threads architected state:</font></tt><br><a href="https://github.com/open-power/sbe/blob/master/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C" target="_blank" ><tt><font face="" size="3" >https://github.com/open-power/sbe/blob/master/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C</font></tt></a><br><br><br><font size="2" >Dean Sanner<br>dsanner@us.ibm.com</font></blockquote>
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