<html><body><p><font size="2">> </font><tt><font size="2">src/bootloader is what produces the hostboot bootloader image</font></tt><br><font size="2">Correct, plus it pulls in a couple shared files from elsewhere, e.g. a couple kernel files and some pnor utilities.</font><br><br><font size="2">> </font><tt><font size="2">src/kernel is what produces the HBB partition</font></tt><br><font size="2">The kernel is a piece of HBB, but not all of it. Basically HBB is all the code required to get access to the PNOR and be able to page in the rest of the code. Everything in HBB is non-pageable, everything in HBI is pageable.</font><br><br><font size="2">> </font><tt><font size="2">kernel_dispatch_task() which is marked as having 'no return',</font></tt><br><font size="2">Correct, that call ends by jumping to a real worker task. After that point the scheduler handles moving things around.</font><br><br><font size="2">> </font><tt><font size="2">how one reads/writes the scom on a power9 system?</font></tt><br><font size="2">The complication is due to the fact that there are many ways to do a scom, depending on where you are executing from and the current state of the system, and also which target you are trying to access. The native method on the processor is called xscom. This is simply a memory-mapped space (BAR is written by SBE) that you do loads/stores to and then look at the HMER for status. See src/usr/xscom/xscom.C :: xScomDoOp() for the bottom of the stack. However, a core can only issue xscoms to processors that are currently part of the SMP fabric since the request flows around the power bus. That means it cannot access anything on the second processor until after istep10. Before that point, you need to use some kind of sideband interface, which is where FSI shows up. If you disable security, you can use the fsi2pib engine in the CFAM logic to do scoms (see src/usr/fsiscom/). Wither security enabled (which is the default), that path is disabled so you have to go through the SBE code to do the scoms. There is a FIFO engine on the FSI bus where we send commands over to the SBE code. All of that logic is in src/usr/sbeio/. Then you can add another layer of confusion when you start accessing the non-processor chips on the system. The code in src/usr/scom/ basically routes a generic 'scom' request to the appropriate low-level transport layer.</font><br><font size="2"><br>--<br>Dan Crowell<br>Senior Software Engineer - Power Systems Enablement Firmware<br>IBM Rochester: t/l 553-2987<br>dcrowell@us.ibm.com</font><br><br><img width="16" height="16" src="cid:1__=09BB0ECDDFDF82068f9e8a93df938690918c09B@" border="0" alt="Inactive hide details for "Marty E. Plummer" ---08/21/2019 06:25:49 PM---Hello. After making some progress coreboot-side on bei"><font size="2" color="#424282">"Marty E. Plummer" ---08/21/2019 06:25:49 PM---Hello. After making some progress coreboot-side on being able to enter their</font><br><br><font size="2" color="#5F5F5F">From: </font><font size="2">"Marty E. Plummer" <hanetzer@startmail.com></font><br><font size="2" color="#5F5F5F">To: </font><font size="2">openpower-firmware@lists.ozlabs.org</font><br><font size="2" color="#5F5F5F">Date: </font><font size="2">08/21/2019 06:25 PM</font><br><font size="2" color="#5F5F5F">Subject: </font><font size="2">[EXTERNAL] [OpenPower-Firmware] Further information about hostboot</font><br><font size="2" color="#5F5F5F">Sent by: </font><font size="2">"OpenPower-Firmware" <openpower-firmware-bounces+dcrowell=us.ibm.com@lists.ozlabs.org></font><br><hr width="100%" size="2" align="left" noshade style="color:#8091A5; "><br><br><br><tt><font size="2">Hello.<br><br>After making some progress coreboot-side on being able to enter their<br>code path using 'stock' seeprom images (I've hopefully put together a<br>way to wrap coreboot.rom in ffs style headers to make hostboot bootloader<br>load our bootblock) I was hoping for some more information on various<br>things.<br><br>So, if I understand correctly, the directory src/bootloader is what<br>produces the hostboot bootloader image on the seeprom, and src/kernel<br>is what produces the HBB partition on the pnor, right? (I've marked the<br>bootblock in coreboot as HBB to make hbbl load it).<br><br>In addition, I'm not sure how src/kernel/kernel.C:106's main function<br>carries on as the last instruction is kernel_dispatch_task() which is<br>marked as having 'no return', am I misunderstanding something?<br><br>Also, could someone elaborate how one reads/writes the scom on a power9<br>system? I'm having trouble following the c++ code involved due to all<br>the indirection. A simple assembly or c example would be quite helpful.<br><br>Regards,<br>Marty<br>_______________________________________________<br>OpenPower-Firmware mailing list<br>OpenPower-Firmware@lists.ozlabs.org<br><a href="https://lists.ozlabs.org/listinfo/openpower-firmware">https://lists.ozlabs.org/listinfo/openpower-firmware</a> <br><br></font></tt><br><br><BR>
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