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Hello,</div>
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I was wondering if anyone is/was successful in using the MCTP over LPC binding with an intel platform? I read through the documents, it seems to me the binding was designed to use LPC firmware cycles. To me it is unclear if the ast2500 supports memory cycles
on the LPC2AHB bridge (datasheet seems to list it in the features, not much explanation). The problem is that the C620 chipset doesn't support firmware cycles (only memory and I/O cycles). And having a properly mapped window in the C620 chipset and reserved
memory in Linux. Writing and Reading to it only returns ('1s').</div>
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Writing a simple test on x86 that keeps writing a value to the mapped registers, seems to trigger LAD[3:1] = 0xF readout on the BMC LPC host controller register 0 (that has some debug registers to see the state of the LPC bus). 0xF is the stop frame of a standard
LPC memory cycle.</div>
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Kind Regards,</div>
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Govert Overgaauw</div>
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