<div dir="ltr"><div dir="ltr">Hi Philipp,<div><br></div><div>Thanks a lot for your comments.</div><div><br></div><div>On Tue, 29 Oct 2019 at 17:34, Philipp Zabel <<a href="mailto:p.zabel@pengutronix.de">p.zabel@pengutronix.de</a>> wrote:<br></div></div><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">On Mon, 2019-10-28 at 17:54 +0200, Tomer Maimon wrote:<br>
> Add Nuvoton NPCM BMC reset controller driver.<br>
> <br>
> Signed-off-by: Tomer Maimon <<a href="mailto:tmaimon77@gmail.com" target="_blank">tmaimon77@gmail.com</a>><br>
> ---<br>
> drivers/reset/Kconfig | 7 +<br>
> drivers/reset/Makefile | 1 +<br>
> drivers/reset/reset-npcm.c | 275 +++++++++++++++++++++++++++++++++++++<br>
> 3 files changed, 283 insertions(+)<br>
> create mode 100644 drivers/reset/reset-npcm.c<br>
> <br>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig<br>
> index 7b07281aa0ae..5dbfdf6d717a 100644<br>
> --- a/drivers/reset/Kconfig<br>
> +++ b/drivers/reset/Kconfig<br>
> @@ -89,6 +89,13 @@ config RESET_MESON_AUDIO_ARB<br>
> This enables the reset driver for Audio Memory Arbiter of<br>
> Amlogic's A113 based SoCs<br>
> <br>
> +config RESET_NPCM<br>
> + bool "NPCM BMC Reset Driver"<br>
> + depends on ARCH_NPCM || COMPILE_TEST<br>
> + help<br>
> + This enables the reset controller driver for Nuvoton NPCM <br>
> + BMC SoCs.<br>
> +<br>
<br>
Is there any reason to ever disable this driver when building ARCH_NPCM?<br>
<br>
> config RESET_OXNAS<br>
> bool<br>
> <br>
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile<br>
> index cf60ce526064..00767c03f5f2 100644<br>
> --- a/drivers/reset/Makefile<br>
> +++ b/drivers/reset/Makefile<br>
> @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o<br>
> obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o<br>
> obj-$(CONFIG_RESET_MESON) += reset-meson.o<br>
> obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o<br>
> +obj-$(CONFIG_RESET_NPCM) += reset-npcm.o<br>
> obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o<br>
> obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o<br>
> obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o<br>
> diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c<br>
> new file mode 100644<br>
> index 000000000000..ebb3071767e1<br>
> --- /dev/null<br>
> +++ b/drivers/reset/reset-npcm.c<br>
> @@ -0,0 +1,275 @@<br>
> +// SPDX-License-Identifier: GPL-2.0<br>
> +// Copyright (c) 2019 Nuvoton Technology corporation.<br>
> +<br>
> +#include <linux/clk.h><br>
<br>
Please remove unused header includes.<br>
<br>
> +#include <linux/delay.h><br>
> +#include <linux/err.h><br>
> +#include <linux/io.h><br>
> +#include <linux/init.h><br>
> +#include <linux/of.h><br>
> +#include <linux/platform_device.h><br>
> +#include <linux/reboot.h><br>
> +#include <linux/reset-controller.h><br>
> +#include <linux/spinlock.h><br>
> +#include <linux/mfd/syscon.h><br>
> +#include <linux/regmap.h><br>
> +#include <linux/of_address.h><br>
> +<br>
> +/* NPCM7xx GCR registers */<br>
> +#define NPCM_MDLR_OFFSET 0x7C<br>
> +#define NPCM_MDLR_USBD0 BIT(9)<br>
> +#define NPCM_MDLR_USBD1 BIT(8)<br>
> +#define NPCM_MDLR_USBD2_4 BIT(21)<br>
> +#define NPCM_MDLR_USBD5_9 BIT(22)<br>
> +<br>
> +#define NPCM_USB1PHYCTL_OFFSET 0x140<br>
> +#define NPCM_USB2PHYCTL_OFFSET 0x144<br>
> +#define NPCM_USBXPHYCTL_RS BIT(28)<br>
> +<br>
> +/* NPCM7xx Reset registers */<br>
> +#define NPCM_SWRSTR 0x14<br>
> +#define NPCM_SWRST BIT(2)<br>
> +<br>
> +#define NPCM_IPSRST1 0x20<br>
> +#define NPCM_IPSRST1_USBD1 BIT(5)<br>
> +#define NPCM_IPSRST1_USBD2 BIT(8)<br>
> +#define NPCM_IPSRST1_USBD3 BIT(25)<br>
> +#define NPCM_IPSRST1_USBD4 BIT(22)<br>
> +#define NPCM_IPSRST1_USBD5 BIT(23)<br>
> +#define NPCM_IPSRST1_USBD6 BIT(24)<br>
> +<br>
> +#define NPCM_IPSRST2 0x24<br>
> +#define NPCM_IPSRST2_USB_HOST BIT(26)<br>
> +<br>
> +#define NPCM_IPSRST3 0x34<br>
> +#define NPCM_IPSRST3_USBD0 BIT(4)<br>
> +#define NPCM_IPSRST3_USBD7 BIT(5)<br>
> +#define NPCM_IPSRST3_USBD8 BIT(6)<br>
> +#define NPCM_IPSRST3_USBD9 BIT(7)<br>
> +#define NPCM_IPSRST3_USBPHY1 BIT(24)<br>
> +#define NPCM_IPSRST3_USBPHY2 BIT(25)<br>
> +<br>
> +#define NPCM_RC_RESETS_PER_REG 32<br>
> +<br>
> +struct npcm_rc_data {<br>
> + struct reset_controller_dev rcdev;<br>
> + struct notifier_block restart_nb;<br>
> + u32 sw_reset_number;<br>
> + void __iomem *base;<br>
> + spinlock_t lock;<br>
> +};<br>
> +<br>
> +#define to_rc_data(p) container_of(p, struct npcm_rc_data, rcdev)<br>
> +<br>
> +static int npcm_rc_restart(struct notifier_block *nb, unsigned long mode,<br>
> + void *cmd)<br>
> +{<br>
> + struct npcm_rc_data *rc = container_of(nb, struct npcm_rc_data,<br>
> + restart_nb);<br>
> +<br>
> + writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR);<br>
> + mdelay(1000);<br>
> +<br>
> + pr_emerg("%s: unable to restart system\n", __func__);<br>
> +<br>
> + return NOTIFY_DONE;<br>
> +}<br>
> +<br>
> +static int npcm_rc_setclear_reset(struct reset_controller_dev *rcdev,<br>
> + unsigned long id, bool set)<br>
> +{<br>
> + struct npcm_rc_data *rc = to_rc_data(rcdev);<br>
> + u32 ctrl_offset = NPCM_IPSRST1;<br>
> + unsigned long flags;<br>
> + u32 stat, rst_bit;<br>
> +<br>
> + ctrl_offset += (id / NPCM_RC_RESETS_PER_REG) * sizeof(u32);<br>
> + rst_bit = 1 << (id % NPCM_RC_RESETS_PER_REG);<br>
> +<br>
> + spin_lock_irqsave(&rc->lock, flags);<br>
> + stat = readl(rc->base + ctrl_offset);<br>
> + if (set)<br>
> + writel(stat | rst_bit, rc->base + ctrl_offset);<br>
> + else<br>
> + writel(stat & ~rst_bit, rc->base + ctrl_offset);<br>
> + spin_unlock_irqrestore(&rc->lock, flags);<br>
> +<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static int npcm_rc_assert(struct reset_controller_dev *rcdev, unsigned long id)<br>
> +{<br>
> + return npcm_rc_setclear_reset(rcdev, id, true);<br>
> +}<br>
> +<br>
> +static int npcm_rc_deassert(struct reset_controller_dev *rcdev,<br>
> + unsigned long id)<br>
> +{<br>
> + return npcm_rc_setclear_reset(rcdev, id, false);<br>
> +}<br>
> +<br>
> +static int npcm_rc_status(struct reset_controller_dev *rcdev,<br>
> + unsigned long id)<br>
> +{<br>
> + struct npcm_rc_data *rc = to_rc_data(rcdev);<br>
> + u32 bit, ctrl_offset = NPCM_IPSRST1;<br>
> +<br>
> + ctrl_offset += (id / NPCM_RC_RESETS_PER_REG) * sizeof(u32);<br>
> + bit = 1 << (id % NPCM_RC_RESETS_PER_REG);<br>
> +<br>
> + return (readl(rc->base + ctrl_offset) & bit);<br>
> +}<br>
> +<br>
> +/*<br>
> + * The following procedure should be observed in USB PHY, USB device and<br>
> + * USB host initialization at BMC boot<br>
> + */<br>
> +static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)<br>
> +{<br>
> + struct device_node *np = pdev->dev.of_node;<br>
> + u32 mdlr, iprst1, iprst2, iprst3;<br>
> + struct regmap *gcr_regmap;<br>
> + u32 ipsrst1_bits = 0;<br>
> + u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;<br>
> + u32 ipsrst3_bits = 0;<br>
> +<br>
> + if (of_device_is_compatible(np, "nuvoton,npcm750-reset")) {<br>
> + gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");<br>
> + if (IS_ERR(gcr_regmap)) {<br>
> + dev_err(&pdev->dev, "Failed to find nuvoton,npcm750-gcr\n");<br>
> + return PTR_ERR(gcr_regmap);<br>
> + }<br>
> + }<br>
> + if (!gcr_regmap)<br>
> + return -ENXIO;<br>
> +<br>
> + /* checking which USB device is enabled */<br>
> + regmap_read(gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);<br>
> + if (!(mdlr & NPCM_MDLR_USBD0))<br>
> + ipsrst3_bits |= NPCM_IPSRST3_USBD0;<br>
> + if (!(mdlr & NPCM_MDLR_USBD1))<br>
> + ipsrst1_bits |= NPCM_IPSRST1_USBD1;<br>
> + if (!(mdlr & NPCM_MDLR_USBD2_4))<br>
> + ipsrst1_bits |= (NPCM_IPSRST1_USBD2 |<br>
> + NPCM_IPSRST1_USBD3 |<br>
> + NPCM_IPSRST1_USBD4);<br>
> + if (!(mdlr & NPCM_MDLR_USBD0)) {<br>
> + ipsrst1_bits |= (NPCM_IPSRST1_USBD5 |<br>
> + NPCM_IPSRST1_USBD6);<br>
> + ipsrst3_bits |= (NPCM_IPSRST3_USBD7 |<br>
> + NPCM_IPSRST3_USBD8 |<br>
> + NPCM_IPSRST3_USBD9);<br>
> + }<br>
> +<br>
> + /* assert reset USB PHY and USB devices */<br>
> + iprst1 = readl(rc->base + NPCM_IPSRST1);<br>
> + iprst2 = readl(rc->base + NPCM_IPSRST2);<br>
> + iprst3 = readl(rc->base + NPCM_IPSRST3);<br>
> +<br>
> + iprst1 |= ipsrst1_bits;<br>
> + iprst2 |= ipsrst2_bits;<br>
> + iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |<br>
> + NPCM_IPSRST3_USBPHY2);<br>
> +<br>
> + writel(iprst1, rc->base + NPCM_IPSRST1);<br>
> + writel(iprst2, rc->base + NPCM_IPSRST2);<br>
> + writel(iprst3, rc->base + NPCM_IPSRST3);<br>
> +<br>
> + /* clear USB PHY RS bit */<br>
> + regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,<br>
> + NPCM_USBXPHYCTL_RS, 0);<br>
> + regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,<br>
> + NPCM_USBXPHYCTL_RS, 0);<br>
> +<br>
> + /* deassert reset USB PHY */<br>
> + iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);<br>
> + writel(iprst3, rc->base + NPCM_IPSRST3);<br>
> +<br>
> + udelay(50);<br>
> +<br>
> + /* set USB PHY RS bit */<br>
> + regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,<br>
> + NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);<br>
> + regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,<br>
> + NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);<br>
> +<br>
> + /* deassert reset USB devices*/<br>
> + iprst1 &= ~ipsrst1_bits;<br>
> + iprst2 &= ~ipsrst2_bits;<br>
> + iprst3 &= ~ipsrst3_bits;<br>
> +<br>
> + writel(iprst1, rc->base + NPCM_IPSRST1);<br>
> + writel(iprst2, rc->base + NPCM_IPSRST2);<br>
> + writel(iprst3, rc->base + NPCM_IPSRST3);<br>
> +<br>
> + return 0;<br>
> +}<br>
<br>
Is there no better place for this, such as USB glue code?</blockquote><div>Sorry, I didn't find a proper place to add it in the USB tree.</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"> <br></blockquote><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
> +static const struct reset_control_ops npcm_rc_ops = {<br>
> + .assert = npcm_rc_assert,<br>
> + .deassert = npcm_rc_deassert,<br>
> + .status = npcm_rc_status,<br>
> +};<br>
> +<br>
> +static int npcm_rc_probe(struct platform_device *pdev)<br>
> +{<br>
> + struct npcm_rc_data *rc;<br>
> + struct resource res;<br>
> + int ret;<br>
> +<br>
> + rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);<br>
> + if (!rc)<br>
> + return -ENOMEM;<br>
> +<br>
> + of_address_to_resource(pdev->dev.of_node, 0, &res);<br>
> + rc->base = devm_ioremap_resource(&pdev->dev, &res);<br>
<br>
Can't you just use<br>
<br>
rc->base = devm_platform_ioremap_resource(pdev, 0);<br>
<br>
here?<br>
<br>
> + if (IS_ERR(rc->base))<br>
> + return PTR_ERR(rc->base);<br>
> +<br>
> + spin_lock_init(&rc->lock);<br>
> +<br>
> + rc->rcdev.owner = THIS_MODULE;<br>
> + rc->rcdev.nr_resets = resource_size(&res) / 4 * BITS_PER_LONG;<br>
<br>
That doesn't seem right. With the ctrl_offset = NPCM_IPSRST1 in<br>
npcm_rc_setclear_reset that would allow access beyond the configured<br>
register range.<br>
<br>
> + rc->rcdev.ops = &npcm_rc_ops;<br>
> + rc->rcdev.of_node = pdev->dev.of_node;<br>
> +<br>
> + platform_set_drvdata(pdev, rc);<br>
> +<br>
> + ret = reset_controller_register(&rc->rcdev);<br>
<br>
ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev);<br>
<br>
> + if (ret) {<br>
> + dev_err(&pdev->dev, "unable to register device\n");<br>
> + return ret;<br>
> + }<br>
> +<br>
> + if (npcm_usb_reset(pdev, rc))<br>
> + dev_warn(&pdev->dev, "NPCM USB reset failed, can cause issues with UDC and USB host\n");<br>
> +<br>
> + if (!of_property_read_u32(pdev->dev.of_node, "nuvoton,sw-reset-number",<br>
> + &rc->sw_reset_number)) {<br>
> + if (rc->sw_reset_number && rc->sw_reset_number < 5) {<br>
> + rc->restart_nb.priority = 192,<br>
> + rc->restart_nb.notifier_call = npcm_rc_restart,<br>
> + ret = register_restart_handler(&rc->restart_nb);<br>
> + if (ret)<br>
> + dev_warn(&pdev->dev, "failed to register restart handler\n");<br>
> + }<br>
> + }<br>
> +<br>
> + pr_info("NPCM RESET driver probed\n");<br>
<br>
It think this is a bit verbose.<br>
<br>
> + return ret;<br>
> +}<br>
> +<br>
> +static const struct of_device_id npcm_rc_match[] = {<br>
> + { .compatible = "nuvoton,npcm750-reset" },<br>
> + { }<br>
> +};<br>
> +<br>
> +static struct platform_driver npcm_rc_driver = {<br>
> + .probe = npcm_rc_probe,<br>
> + .driver = {<br>
> + .name = "npcm-reset",<br>
> + .of_match_table = npcm_rc_match,<br>
> + .suppress_bind_attrs = true,<br>
> + },<br>
> +};<br>
> +builtin_platform_driver(npcm_rc_driver);<br>
<br>
regards<br>
Philipp<br>
<br></blockquote><div><br></div><div>Regards,</div><div><br></div><div>Tomer </div></div></div>