<div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Fri, 9 Aug 2019 at 21:02, Benjamin Fair <<a href="mailto:benjaminfair@google.com">benjaminfair@google.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">On Thu, Aug 8, 2019 at 6:15 AM Tomer Maimon <<a href="mailto:tmaimon77@gmail.com" target="_blank">tmaimon77@gmail.com</a>> wrote:<br>
><br>
> Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master<br>
> controller driver using SPI-MEM interface.<br>
><br>
> The FIU supports single, dual or quad communication interface.<br>
><br>
> the FIU controller can operate in following modes:<br>
> - User Mode Access(UMA): provides flash access by using an<br>
> indirect address/data mechanism.<br>
> - direct rd/wr mode: maps the flash memory into the core<br>
> address space.<br>
> - SPI-X mode: used for an expansion bus to an ASIC or CPLD.<br>
><br>
> Signed-off-by: Tomer Maimon <<a href="mailto:tmaimon77@gmail.com" target="_blank">tmaimon77@gmail.com</a>><br>
> ---<br>
> drivers/spi/Kconfig | 10 +<br>
> drivers/spi/Makefile | 1 +<br>
> drivers/spi/spi-npcm-fiu.c | 761 +++++++++++++++++++++++++++++++++++++<br>
> 3 files changed, 772 insertions(+)<br>
> create mode 100644 drivers/spi/spi-npcm-fiu.c<br>
><br>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig<br>
> index 3a1d8f1170de..6ee514fd0920 100644<br>
> --- a/drivers/spi/Kconfig<br>
> +++ b/drivers/spi/Kconfig<br>
> @@ -433,6 +433,16 @@ config SPI_MT7621<br>
> help<br>
> This selects a driver for the MediaTek MT7621 SPI Controller.<br>
><br>
> +config SPI_NPCM_FIU<br>
> + tristate "Nuvoton NPCM FLASH Interface Unit"<br>
> + depends on ARCH_NPCM || COMPILE_TEST<br>
> + depends on OF && HAS_IOMEM<br>
> + help<br>
> + This enables support for the Flash Interface Unit SPI controller<br>
> + in master mode.<br>
> + This driver does not support generic SPI. The implementation only<br>
> + supports spi-mem interface.<br>
> +<br>
> config SPI_NPCM_PSPI<br>
> tristate "Nuvoton NPCM PSPI Controller"<br>
> depends on ARCH_NPCM || COMPILE_TEST<br>
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile<br>
> index 63dcab552bcb..adbebee93a75 100644<br>
> --- a/drivers/spi/Makefile<br>
> +++ b/drivers/spi/Makefile<br>
> @@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o<br>
> obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o<br>
> obj-$(CONFIG_SPI_MXIC) += spi-mxic.o<br>
> obj-$(CONFIG_SPI_MXS) += spi-mxs.o<br>
> +obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o<br>
> obj-$(CONFIG_SPI_NPCM_PSPI) += spi-npcm-pspi.o<br>
> obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o<br>
> obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o<br>
> diff --git a/drivers/spi/spi-npcm-fiu.c b/drivers/spi/spi-npcm-fiu.c<br>
> new file mode 100644<br>
> index 000000000000..2d8c281e8fa9<br>
> --- /dev/null<br>
> +++ b/drivers/spi/spi-npcm-fiu.c<br>
> @@ -0,0 +1,761 @@<br>
> +// SPDX-License-Identifier: GPL-2.0<br>
> +// Copyright (c) 2019 Nuvoton Technology corporation.<br>
> +<br>
> +#include <linux/init.h><br>
> +#include <linux/kernel.h><br>
> +#include <linux/device.h><br>
> +#include <linux/module.h><br>
> +#include <linux/ioport.h><br>
> +#include <linux/clk.h><br>
> +#include <linux/platform_device.h><br>
> +#include <linux/io.h><br>
> +#include <linux/vmalloc.h><br>
> +#include <linux/regmap.h><br>
> +#include <linux/of_device.h><br>
> +#include <linux/spi/spi-mem.h><br>
> +#include <linux/mfd/syscon.h><br>
> +<br>
> +/* NPCM7xx GCR module */<br>
> +#define NPCM7XX_INTCR3_OFFSET 0x9C<br>
> +#define NPCM7XX_INTCR3_FIU_FIX BIT(6)<br>
> +<br>
> +/* Flash Interface Unit (FIU) Registers */<br>
> +#define NPCM_FIU_DRD_CFG 0x00<br>
> +#define NPCM_FIU_DWR_CFG 0x04<br>
> +#define NPCM_FIU_UMA_CFG 0x08<br>
> +#define NPCM_FIU_UMA_CTS 0x0C<br>
> +#define NPCM_FIU_UMA_CMD 0x10<br>
> +#define NPCM_FIU_UMA_ADDR 0x14<br>
> +#define NPCM_FIU_PRT_CFG 0x18<br>
> +#define NPCM_FIU_UMA_DW0 0x20<br>
> +#define NPCM_FIU_UMA_DW1 0x24<br>
> +#define NPCM_FIU_UMA_DW2 0x28<br>
> +#define NPCM_FIU_UMA_DW3 0x2C<br>
> +#define NPCM_FIU_UMA_DR0 0x30<br>
> +#define NPCM_FIU_UMA_DR1 0x34<br>
> +#define NPCM_FIU_UMA_DR2 0x38<br>
> +#define NPCM_FIU_UMA_DR3 0x3C<br>
> +#define NPCM_FIU_MAX_REG_LIMIT 0x80<br>
> +<br>
> +/* FIU Direct Read Configuration Register */<br>
> +#define NPCM_FIU_DRD_CFG_LCK BIT(31)<br>
> +#define NPCM_FIU_DRD_CFG_R_BURST GENMASK(25, 24)<br>
> +#define NPCM_FIU_DRD_CFG_ADDSIZ GENMASK(17, 16)<br>
> +#define NPCM_FIU_DRD_CFG_DBW GENMASK(13, 12)<br>
> +#define NPCM_FIU_DRD_CFG_ACCTYPE GENMASK(9, 8)<br>
> +#define NPCM_FIU_DRD_CFG_RDCMD GENMASK(7, 0)<br>
> +#define NPCM_FIU_DRD_ADDSIZ_SHIFT 16<br>
> +#define NPCM_FIU_DRD_DBW_SHIFT 12<br>
> +#define NPCM_FIU_DRD_ACCTYPE_SHIFT 8<br>
> +<br>
> +/* FIU Direct Write Configuration Register */<br>
> +#define NPCM_FIU_DWR_CFG_LCK BIT(31)<br>
> +#define NPCM_FIU_DWR_CFG_W_BURST GENMASK(25, 24)<br>
> +#define NPCM_FIU_DWR_CFG_ADDSIZ GENMASK(17, 16)<br>
> +#define NPCM_FIU_DWR_CFG_ABPCK GENMASK(11, 10)<br>
> +#define NPCM_FIU_DWR_CFG_DBPCK GENMASK(9, 8)<br>
> +#define NPCM_FIU_DWR_CFG_WRCMD GENMASK(7, 0)<br>
> +#define NPCM_FIU_DWR_ADDSIZ_SHIFT 16<br>
> +#define NPCM_FIU_DWR_ABPCK_SHIFT 10<br>
> +#define NPCM_FIU_DWR_DBPCK_SHIFT 8<br>
> +<br>
> +/* FIU UMA Configuration Register */<br>
> +#define NPCM_FIU_UMA_CFG_LCK BIT(31)<br>
> +#define NPCM_FIU_UMA_CFG_CMMLCK BIT(30)<br>
> +#define NPCM_FIU_UMA_CFG_RDATSIZ GENMASK(28, 24)<br>
> +#define NPCM_FIU_UMA_CFG_DBSIZ GENMASK(23, 21)<br>
> +#define NPCM_FIU_UMA_CFG_WDATSIZ GENMASK(20, 16)<br>
> +#define NPCM_FIU_UMA_CFG_ADDSIZ GENMASK(13, 11)<br>
> +#define NPCM_FIU_UMA_CFG_CMDSIZ BIT(10)<br>
> +#define NPCM_FIU_UMA_CFG_RDBPCK GENMASK(9, 8)<br>
> +#define NPCM_FIU_UMA_CFG_DBPCK GENMASK(7, 6)<br>
> +#define NPCM_FIU_UMA_CFG_WDBPCK GENMASK(5, 4)<br>
> +#define NPCM_FIU_UMA_CFG_ADBPCK GENMASK(3, 2)<br>
> +#define NPCM_FIU_UMA_CFG_CMBPCK GENMASK(1, 0)<br>
> +#define NPCM_FIU_UMA_CFG_ADBPCK_SHIFT 2<br>
> +#define NPCM_FIU_UMA_CFG_WDBPCK_SHIFT 4<br>
> +#define NPCM_FIU_UMA_CFG_DBPCK_SHIFT 6<br>
> +#define NPCM_FIU_UMA_CFG_RDBPCK_SHIFT 8<br>
> +#define NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT 11<br>
> +#define NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT 16<br>
> +#define NPCM_FIU_UMA_CFG_DBSIZ_SHIFT 21<br>
> +#define NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT 24<br>
> +<br>
> +/* FIU UMA Control and Status Register */<br>
> +#define NPCM_FIU_UMA_CTS_RDYIE BIT(25)<br>
> +#define NPCM_FIU_UMA_CTS_RDYST BIT(24)<br>
> +#define NPCM_FIU_UMA_CTS_SW_CS BIT(16)<br>
> +#define NPCM_FIU_UMA_CTS_DEV_NUM GENMASK(9, 8)<br>
> +#define NPCM_FIU_UMA_CTS_EXEC_DONE BIT(0)<br>
> +#define NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT 8<br>
> +<br>
> +/* FIU UMA Command Register */<br>
> +#define NPCM_FIU_UMA_CMD_DUM3 GENMASK(31, 24)<br>
> +#define NPCM_FIU_UMA_CMD_DUM2 GENMASK(23, 16)<br>
> +#define NPCM_FIU_UMA_CMD_DUM1 GENMASK(15, 8)<br>
> +#define NPCM_FIU_UMA_CMD_CMD GENMASK(7, 0)<br>
> +<br>
> +/* FIU UMA Address Register */<br>
> +#define NPCM_FIU_UMA_ADDR_UMA_ADDR GENMASK(31, 0)<br>
> +#define NPCM_FIU_UMA_ADDR_AB3 GENMASK(31, 24)<br>
> +#define NPCM_FIU_UMA_ADDR_AB2 GENMASK(23, 16)<br>
> +#define NPCM_FIU_UMA_ADDR_AB1 GENMASK(15, 8)<br>
> +#define NPCM_FIU_UMA_ADDR_AB0 GENMASK(7, 0)<br>
> +<br>
> +/* FIU UMA Write Data Bytes 0-3 Register */<br>
> +#define NPCM_FIU_UMA_DW0_WB3 GENMASK(31, 24)<br>
> +#define NPCM_FIU_UMA_DW0_WB2 GENMASK(23, 16)<br>
> +#define NPCM_FIU_UMA_DW0_WB1 GENMASK(15, 8)<br>
> +#define NPCM_FIU_UMA_DW0_WB0 GENMASK(7, 0)<br>
> +<br>
> +/* FIU UMA Write Data Bytes 4-7 Register */<br>
> +#define NPCM_FIU_UMA_DW1_WB7 GENMASK(31, 24)<br>
> +#define NPCM_FIU_UMA_DW1_WB6 GENMASK(23, 16)<br>
> +#define NPCM_FIU_UMA_DW1_WB5 GENMASK(15, 8)<br>
> +#define NPCM_FIU_UMA_DW1_WB4 GENMASK(7, 0)<br>
> +<br>
> +/* FIU UMA Write Data Bytes 8-11 Register */<br>
> +#define NPCM_FIU_UMA_DW2_WB11 GENMASK(31, 24)<br>
> +#define NPCM_FIU_UMA_DW2_WB10 GENMASK(23, 16)<br>
> +#define NPCM_FIU_UMA_DW2_WB9 GENMASK(15, 8)<br>
> +#define NPCM_FIU_UMA_DW2_WB8 GENMASK(7, 0)<br>
> +<br>
> +/* FIU UMA Write Data Bytes 12-15 Register */<br>
> +#define NPCM_FIU_UMA_DW3_WB15 GENMASK(31, 24)<br>
> +#define NPCM_FIU_UMA_DW3_WB14 GENMASK(23, 16)<br>
> +#define NPCM_FIU_UMA_DW3_WB13 GENMASK(15, 8)<br>
> +#define NPCM_FIU_UMA_DW3_WB12 GENMASK(7, 0)<br>
> +<br>
> +/* FIU UMA Read Data Bytes 0-3 Register */<br>
> +#define NPCM_FIU_UMA_DR0_RB3 GENMASK(31, 24)<br>
> +#define NPCM_FIU_UMA_DR0_RB2 GENMASK(23, 16)<br>
> +#define NPCM_FIU_UMA_DR0_RB1 GENMASK(15, 8)<br>
> +#define NPCM_FIU_UMA_DR0_RB0 GENMASK(7, 0)<br>
> +<br>
> +/* FIU UMA Read Data Bytes 4-7 Register */<br>
> +#define NPCM_FIU_UMA_DR1_RB15 GENMASK(31, 24)<br>
> +#define NPCM_FIU_UMA_DR1_RB14 GENMASK(23, 16)<br>
> +#define NPCM_FIU_UMA_DR1_RB13 GENMASK(15, 8)<br>
> +#define NPCM_FIU_UMA_DR1_RB12 GENMASK(7, 0)<br>
> +<br>
> +/* FIU UMA Read Data Bytes 8-11 Register */<br>
> +#define NPCM_FIU_UMA_DR2_RB15 GENMASK(31, 24)<br>
> +#define NPCM_FIU_UMA_DR2_RB14 GENMASK(23, 16)<br>
> +#define NPCM_FIU_UMA_DR2_RB13 GENMASK(15, 8)<br>
> +#define NPCM_FIU_UMA_DR2_RB12 GENMASK(7, 0)<br>
> +<br>
> +/* FIU UMA Read Data Bytes 12-15 Register */<br>
> +#define NPCM_FIU_UMA_DR3_RB15 GENMASK(31, 24)<br>
> +#define NPCM_FIU_UMA_DR3_RB14 GENMASK(23, 16)<br>
> +#define NPCM_FIU_UMA_DR3_RB13 GENMASK(15, 8)<br>
> +#define NPCM_FIU_UMA_DR3_RB12 GENMASK(7, 0)<br>
> +<br>
> +/* FIU Read Mode */<br>
> +enum {<br>
> + DRD_SINGLE_WIRE_MODE = 0,<br>
> + DRD_DUAL_IO_MODE = 1,<br>
> + DRD_QUAD_IO_MODE = 2,<br>
> + DRD_SPI_X_MODE = 3,<br>
> +};<br>
> +<br>
> +enum {<br>
> + DWR_ABPCK_BIT_PER_CLK = 0,<br>
> + DWR_ABPCK_2_BIT_PER_CLK = 1,<br>
> + DWR_ABPCK_4_BIT_PER_CLK = 2,<br>
> +};<br>
> +<br>
> +enum {<br>
> + DWR_DBPCK_BIT_PER_CLK = 0,<br>
> + DWR_DBPCK_2_BIT_PER_CLK = 1,<br>
> + DWR_DBPCK_4_BIT_PER_CLK = 2,<br>
> +};<br>
> +<br>
> +#define NPCM_FIU_DRD_16_BYTE_BURST 0x3000000<br>
> +#define NPCM_FIU_DWR_16_BYTE_BURST 0x3000000<br>
> +<br>
> +#define MAP_SIZE_128MB 0x8000000<br>
> +#define MAP_SIZE_16MB 0x1000000<br>
> +#define MAP_SIZE_8MB 0x800000<br>
> +<br>
> +#define NUM_BITS_IN_BYTE 8<br>
> +#define FIU_DRD_MAX_DUMMY_NUMBER 3<br>
> +#define NPCM_MAX_CHIP_NUM 4<br>
> +#define CHUNK_SIZE 16<br>
> +#define UMA_MICRO_SEC_TIMEOUT 150<br>
> +<br>
> +enum {<br>
> + FIU0 = 0,<br>
> + FIU3,<br>
> + FIUX,<br>
> +};<br>
> +<br>
> +struct npcm_fiu_info {<br>
> + char *name;<br>
> + u32 fiu_id;<br>
> + u32 max_map_size;<br>
> + u32 max_cs;<br>
> +};<br>
> +<br>
> +struct fiu_data {<br>
> + const struct npcm_fiu_info *npcm_fiu_data_info;<br>
> + int fiu_max;<br>
> +};<br>
> +<br>
> +static const struct npcm_fiu_info npxm7xx_fiu_info[] = {<br>
> + {.name = "FIU0", .fiu_id = FIU0,<br>
> + .max_map_size = MAP_SIZE_128MB, .max_cs = 2},<br>
> + {.name = "FIU3", .fiu_id = FIU3,<br>
> + .max_map_size = MAP_SIZE_128MB, .max_cs = 4},<br>
> + {.name = "FIUX", .fiu_id = FIUX,<br>
> + .max_map_size = MAP_SIZE_16MB, .max_cs = 2} };<br>
> +<br>
> +static const struct fiu_data npxm7xx_fiu_data = {<br>
> + .npcm_fiu_data_info = npxm7xx_fiu_info,<br>
> + .fiu_max = 3,<br>
> +};<br>
> +<br>
> +struct npcm_fiu_spi;<br>
> +<br>
> +struct npcm_fiu_chip {<br>
> + void __iomem *flash_region_mapped_ptr;<br>
> + struct npcm_fiu_spi *fiu;<br>
> + unsigned long clkrate;<br>
> + u32 chipselect;<br>
> +};<br>
> +<br>
> +struct npcm_fiu_spi {<br>
> + struct npcm_fiu_chip chip[NPCM_MAX_CHIP_NUM];<br>
> + const struct npcm_fiu_info *info;<br>
> + struct spi_mem_op drd_op;<br>
> + struct resource *res_mem;<br>
> + struct regmap *regmap;<br>
> + unsigned long clkrate;<br>
> + struct device *dev;<br>
> + struct clk *clk;<br>
> + bool spix_mode;<br>
> +};<br>
> +<br>
> +static const struct regmap_config npcm_mtd_regmap_config = {<br>
> + .reg_bits = 32,<br>
> + .val_bits = 32,<br>
> + .reg_stride = 4,<br>
> + .max_register = NPCM_FIU_MAX_REG_LIMIT,<br>
> +};<br>
> +<br>
> +static void npcm_fiu_set_drd(struct npcm_fiu_spi *fiu,<br>
> + const struct spi_mem_op *op)<br>
> +{<br>
> + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,<br>
> + NPCM_FIU_DRD_CFG_ACCTYPE,<br>
> + ilog2(op->addr.buswidth) <<<br>
> + NPCM_FIU_DRD_ACCTYPE_SHIFT);<br>
> + fiu->drd_op.addr.buswidth = op->addr.buswidth;<br>
> + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,<br>
> + NPCM_FIU_DRD_CFG_DBW,<br>
> + ((op->dummy.nbytes * ilog2(op->addr.buswidth))<br>
> + / NUM_BITS_IN_BYTE) << NPCM_FIU_DRD_DBW_SHIFT);<br>
> + fiu->drd_op.dummy.nbytes = op->dummy.nbytes;<br>
> + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,<br>
> + NPCM_FIU_DRD_CFG_RDCMD, op->cmd.opcode);<br>
> + fiu->drd_op.cmd.opcode = op->cmd.opcode;<br>
> + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,<br>
> + NPCM_FIU_DRD_CFG_ADDSIZ,<br>
> + (op->addr.nbytes - 3) << NPCM_FIU_DRD_ADDSIZ_SHIFT);<br>
> + fiu->drd_op.addr.nbytes = op->addr.nbytes;<br>
> +}<br>
> +<br>
> +static ssize_t npcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc,<br>
> + u64 offs, size_t len, void *buf)<br>
> +{<br>
> + struct npcm_fiu_spi *fiu =<br>
> + spi_controller_get_devdata(desc->mem->spi->master);<br>
> + struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];<br>
> + void __iomem *src = (void __iomem *)(chip->flash_region_mapped_ptr +<br>
> + offs);<br>
> + u8 *buf_rx = buf;<br>
> + u32 i;<br>
> +<br>
> + if (fiu->spix_mode) {<br>
> + for (i = 0 ; i < len ; i++)<br>
> + *(buf_rx + i) = ioread8(src + i);<br>
> + } else {<br>
> + if (desc->info.op_tmpl.addr.buswidth != fiu->drd_op.addr.buswidth ||<br>
> + desc->info.op_tmpl.dummy.nbytes != fiu->drd_op.dummy.nbytes ||<br>
> + desc->info.op_tmpl.cmd.opcode != fiu->drd_op.cmd.opcode ||<br>
> + desc->info.op_tmpl.addr.nbytes != fiu->drd_op.addr.nbytes)<br>
> + npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);<br>
> +<br>
> + memcpy_fromio(buf_rx, src, len);<br>
<br>
Does this need to make sure the memcpy is aligned, or is that handled<br>
at a higher layer?<br></blockquote><div> </div><div>The memcpy_fromio use in the direct functions can deal with unaligned address, we have stress test it for some time<br></div><div>and it working well, I have sent Kun the test stress scripts.</div><div><br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<br>
> + }<br>
> +<br>
> + return len;<br>
> +}<br>
> +<br>
> +static ssize_t npcm_fiu_direct_write(struct spi_mem_dirmap_desc *desc,<br>
> + u64 offs, size_t len, const void *buf)<br>
> +{<br>
> + struct npcm_fiu_spi *fiu =<br>
> + spi_controller_get_devdata(desc->mem->spi->master);<br>
> + struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];<br>
> + void __iomem *dst = (void __iomem *)(chip->flash_region_mapped_ptr +<br>
> + offs);<br>
> + const u8 *buf_tx = buf;<br>
> + u32 i;<br>
> +<br>
> + if (fiu->spix_mode)<br>
> + for (i = 0 ; i < len ; i++)<br>
> + iowrite8(*(buf_tx + i), dst + i);<br>
> + else<br>
> + memcpy_toio(dst, buf_tx, len);<br>
> +<br>
> + return len;<br>
> +}<br>
> +<br>
> +static int npcm_fiu_uma_read(struct spi_mem *mem,<br>
> + const struct spi_mem_op *op, u32 addr,<br>
> + bool is_address_size, u8 *data, u32 data_size)<br>
> +{<br>
> + struct npcm_fiu_spi *fiu =<br>
> + spi_controller_get_devdata(mem->spi->master);<br>
> + u32 uma_cfg = BIT(10);<br>
> + u32 data_reg[4];<br>
> + int ret;<br>
> + u32 val;<br>
> + u32 i;<br>
> +<br>
> + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,<br>
> + NPCM_FIU_UMA_CTS_DEV_NUM,<br>
> + (mem->spi->chip_select <<<br>
> + NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));<br>
> + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD,<br>
> + NPCM_FIU_UMA_CMD_CMD, op->cmd.opcode);<br>
> +<br>
> + if (is_address_size) {<br>
> + uma_cfg |= ilog2(op->cmd.buswidth);<br>
> + uma_cfg |= ilog2(op->addr.buswidth)<br>
> + << NPCM_FIU_UMA_CFG_ADBPCK_SHIFT;<br>
> + uma_cfg |= ilog2(op->dummy.buswidth)<br>
> + << NPCM_FIU_UMA_CFG_DBPCK_SHIFT;<br>
> + uma_cfg |= ilog2(op->data.buswidth)<br>
> + << NPCM_FIU_UMA_CFG_RDBPCK_SHIFT;<br>
> + uma_cfg |= op->dummy.nbytes << NPCM_FIU_UMA_CFG_DBSIZ_SHIFT;<br>
> + uma_cfg |= op->addr.nbytes << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT;<br>
> + regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, addr);<br>
> + } else {<br>
> + regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0);<br>
> + }<br>
> +<br>
> + uma_cfg |= data_size << NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT;<br>
> + regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg);<br>
> + regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS,<br>
> + NPCM_FIU_UMA_CTS_EXEC_DONE,<br>
> + NPCM_FIU_UMA_CTS_EXEC_DONE);<br>
> + ret = regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val,<br>
> + (!(val & NPCM_FIU_UMA_CTS_EXEC_DONE)), 0,<br>
> + UMA_MICRO_SEC_TIMEOUT);<br>
> + if (ret)<br>
> + return ret;<br>
> +<br>
> + if (data_size) {<br>
> + for (i = 0; i < DIV_ROUND_UP(data_size, 4); i++)<br>
> + regmap_read(fiu->regmap, NPCM_FIU_UMA_DR0 + (i * 4),<br>
> + &data_reg[i]);<br>
> + memcpy(data, data_reg, data_size);<br>
> + }<br>
> +<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static int npcm_fiu_uma_write(struct spi_mem *mem,<br>
> + const struct spi_mem_op *op, u8 cmd,<br>
> + bool is_address_size, u8 *data, u32 data_size)<br>
> +{<br>
> + struct npcm_fiu_spi *fiu =<br>
> + spi_controller_get_devdata(mem->spi->master);<br>
> + u32 uma_cfg = BIT(10);<br>
> + u32 data_reg[4] = {0};<br>
> + u32 val;<br>
> + u32 i;<br>
> +<br>
> + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,<br>
> + NPCM_FIU_UMA_CTS_DEV_NUM,<br>
> + (mem->spi->chip_select <<<br>
> + NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));<br>
> +<br>
> + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD,<br>
> + NPCM_FIU_UMA_CMD_CMD, cmd);<br>
> +<br>
> + if (data_size) {<br>
> + memcpy(data_reg, data, data_size);<br>
> + for (i = 0; i < DIV_ROUND_UP(data_size, 4); i++)<br>
> + regmap_write(fiu->regmap, NPCM_FIU_UMA_DW0 + (i * 4),<br>
> + data_reg[i]);<br>
> + }<br>
> +<br>
> + if (is_address_size) {<br>
> + uma_cfg |= ilog2(op->cmd.buswidth);<br>
> + uma_cfg |= ilog2(op->addr.buswidth) <<<br>
> + NPCM_FIU_UMA_CFG_ADBPCK_SHIFT;<br>
> + uma_cfg |= ilog2(op->data.buswidth) <<<br>
> + NPCM_FIU_UMA_CFG_WDBPCK_SHIFT;<br>
> + uma_cfg |= op->addr.nbytes << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT;<br>
> + regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, op->addr.val);<br>
> + } else {<br>
> + regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0);<br>
> + }<br>
> +<br>
> + uma_cfg |= (data_size << NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT);<br>
> + regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg);<br>
> +<br>
> + regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS,<br>
> + NPCM_FIU_UMA_CTS_EXEC_DONE,<br>
> + NPCM_FIU_UMA_CTS_EXEC_DONE);<br>
> +<br>
> + return regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val,<br>
> + (!(val & NPCM_FIU_UMA_CTS_EXEC_DONE)), 0,<br>
> + UMA_MICRO_SEC_TIMEOUT);<br>
> +}<br>
> +<br>
> +static int npcm_fiu_manualwrite(struct spi_mem *mem,<br>
> + const struct spi_mem_op *op)<br>
> +{<br>
> + struct npcm_fiu_spi *fiu =<br>
> + spi_controller_get_devdata(mem->spi->master);<br>
> + u8 *data = (u8 *)op->data.buf.out;<br>
> + u32 num_data_chunks;<br>
> + u32 remain_data;<br>
> + u32 idx = 0;<br>
> + int ret;<br>
> +<br>
> + num_data_chunks = op->data.nbytes / CHUNK_SIZE;<br>
> + remain_data = op->data.nbytes % CHUNK_SIZE;<br>
> +<br>
> + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,<br>
> + NPCM_FIU_UMA_CTS_DEV_NUM,<br>
> + (mem->spi->chip_select <<<br>
> + NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));<br>
> + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,<br>
> + NPCM_FIU_UMA_CTS_SW_CS, 0);<br>
> +<br>
> + ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, true, NULL, 0);<br>
> + if (ret)<br>
> + return ret;<br>
> +<br>
> + /* Starting the data writing loop in multiples of 8 */<br>
> + for (idx = 0; idx < num_data_chunks; ++idx) {<br>
> + ret = npcm_fiu_uma_write(mem, op, data[0], false,<br>
> + &data[1], CHUNK_SIZE - 1);<br>
> + if (ret)<br>
> + return ret;<br>
> +<br>
> + data += CHUNK_SIZE;<br>
> + }<br>
> +<br>
> + /* Handling chunk remains */<br>
> + if (remain_data > 0) {<br>
> + ret = npcm_fiu_uma_write(mem, op, data[0], false,<br>
> + &data[1], remain_data - 1);<br>
> + if (ret)<br>
> + return ret;<br>
> + }<br>
> +<br>
> + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,<br>
> + NPCM_FIU_UMA_CTS_SW_CS, NPCM_FIU_UMA_CTS_SW_CS);<br>
> +<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static int npcm_fiu_read(struct spi_mem *mem, const struct spi_mem_op *op)<br>
> +{<br>
> + u8 *data = op-><a href="http://data.buf.in" rel="noreferrer" target="_blank">data.buf.in</a>;<br>
> + int i, readlen, currlen;<br>
> + size_t retlen = 0;<br>
> + u8 *buf_ptr;<br>
> + u32 addr;<br>
> + int ret;<br>
> +<br>
> + i = 0;<br>
> + currlen = op->data.nbytes;<br>
> +<br>
> + do {<br>
> + addr = ((u32)op->addr.val + i);<br>
> + if (currlen < 16)<br>
> + readlen = currlen;<br>
> + else<br>
> + readlen = 16;<br>
> +<br>
> + buf_ptr = data + i;<br>
> + ret = npcm_fiu_uma_read(mem, op, addr, true, buf_ptr,<br>
> + readlen);<br>
> + if (ret)<br>
> + return ret;<br>
> +<br>
> + i += readlen;<br>
> + currlen -= 16;<br>
> + } while (currlen > 0);<br>
> +<br>
> + retlen = i;<br>
> +<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static void npcm_fiux_set_direct_wr(struct npcm_fiu_spi *fiu)<br>
> +{<br>
> + regmap_write(fiu->regmap, NPCM_FIU_DWR_CFG,<br>
> + NPCM_FIU_DWR_16_BYTE_BURST);<br>
> + regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG,<br>
> + NPCM_FIU_DWR_CFG_ABPCK,<br>
> + DWR_ABPCK_4_BIT_PER_CLK << NPCM_FIU_DWR_ABPCK_SHIFT);<br>
> + regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG,<br>
> + NPCM_FIU_DWR_CFG_DBPCK,<br>
> + DWR_DBPCK_4_BIT_PER_CLK << NPCM_FIU_DWR_DBPCK_SHIFT);<br>
> +}<br>
> +<br>
> +static void npcm_fiux_set_direct_rd(struct npcm_fiu_spi *fiu)<br>
> +{<br>
> + u32 rx_dummy = 0;<br>
> +<br>
> + regmap_write(fiu->regmap, NPCM_FIU_DRD_CFG,<br>
> + NPCM_FIU_DRD_16_BYTE_BURST);<br>
> + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,<br>
> + NPCM_FIU_DRD_CFG_ACCTYPE,<br>
> + DRD_SPI_X_MODE << NPCM_FIU_DRD_ACCTYPE_SHIFT);<br>
> + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,<br>
> + NPCM_FIU_DRD_CFG_DBW,<br>
> + rx_dummy << NPCM_FIU_DRD_DBW_SHIFT);<br>
> +}<br>
> +<br>
> +static int npcm_fiu_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)<br>
> +{<br>
> + struct npcm_fiu_spi *fiu =<br>
> + spi_controller_get_devdata(mem->spi->master);<br>
> + struct npcm_fiu_chip *chip = &fiu->chip[mem->spi->chip_select];<br>
> + int ret = 0;<br>
> + u8 *buf;<br>
> +<br>
> + dev_dbg(fiu->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",<br>
> + op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,<br>
> + op->dummy.buswidth, op->data.buswidth, op->addr.val,<br>
> + op->data.nbytes);<br>
> +<br>
> + if (fiu->spix_mode)<br>
> + return -ENOTSUPP;<br>
> +<br>
> + if (fiu->clkrate != chip->clkrate) {<br>
> + ret = clk_set_rate(fiu->clk, chip->clkrate);<br>
> + if (ret < 0)<br>
> + dev_warn(fiu->dev, "Failed setting %lu frequancy, stay at %lu frequancy\n", chip->clkrate, fiu->clkrate);<br>
> + else<br>
> + fiu->clkrate = chip->clkrate;<br>
> + }<br>
> +<br>
> + if (op->data.dir == SPI_MEM_DATA_IN) {<br>
> + if (!op->addr.nbytes) {<br>
> + buf = op-><a href="http://data.buf.in" rel="noreferrer" target="_blank">data.buf.in</a>;<br>
> + ret = npcm_fiu_uma_read(mem, op, op->addr.val, false,<br>
> + buf, op->data.nbytes);<br>
> + } else {<br>
> + ret = npcm_fiu_read(mem, op);<br>
> + }<br>
> + } else {<br>
> + if (!op->addr.nbytes || !op->data.nbytes) {<br>
> + if (op->data.nbytes)<br>
> + buf = (u8 *)op->data.buf.out;<br>
> + else<br>
> + buf = NULL;<br>
> + ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false,<br>
> + buf, op->data.nbytes);<br>
> + } else {<br>
> + ret = npcm_fiu_manualwrite(mem, op);<br>
> + }<br>
> + }<br>
> +<br>
> + return ret;<br>
> +}<br>
> +<br>
> +static int npcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc)<br>
> +{<br>
> + struct npcm_fiu_spi *fiu =<br>
> + spi_controller_get_devdata(desc->mem->spi->master);<br>
> + struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];<br>
> + struct regmap *gcr_regmap;<br>
> +<br>
> + if (!fiu->res_mem) {<br>
> + dev_warn(fiu->dev, "Reserved memory not defined, direct read disabled\n");<br>
> + desc->nodirmap = true;<br>
> + return 0;<br>
> + }<br>
> +<br>
> + if (!fiu->spix_mode &&<br>
> + desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) {<br>
> + desc->nodirmap = true;<br>
> + return 0;<br>
> + }<br>
> +<br>
> + if (!chip->flash_region_mapped_ptr) {<br>
> + chip->flash_region_mapped_ptr =<br>
> + devm_ioremap_nocache(fiu->dev, (fiu->res_mem->start +<br>
> + (fiu->info->max_map_size *<br>
> + desc->mem->spi->chip_select)),<br>
> + (u32)desc->info.length);<br>
> + if (!chip->flash_region_mapped_ptr) {<br>
> + dev_warn(fiu->dev, "Error mapping memory region, direct read disabled\n");<br>
> + desc->nodirmap = true;<br>
> + return 0;<br>
> + }<br>
> + }<br>
> +<br>
> + if (of_device_is_compatible(fiu->dev->of_node, "nuvoton,npcm750-fiu")) {<br>
> + gcr_regmap =<br>
> + syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");<br>
> + if (IS_ERR(gcr_regmap)) {<br>
> + dev_warn(fiu->dev, "Didn't find nuvoton,npcm750-gcr, direct read disabled\n");<br>
> + desc->nodirmap = true;<br>
> + return 0;<br>
> + }<br>
> + regmap_update_bits(gcr_regmap, NPCM7XX_INTCR3_OFFSET,<br>
> + NPCM7XX_INTCR3_FIU_FIX,<br>
> + NPCM7XX_INTCR3_FIU_FIX);<br>
> + }<br>
> +<br>
> + if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) {<br>
> + if (!fiu->spix_mode)<br>
> + npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);<br>
> + else<br>
> + npcm_fiux_set_direct_rd(fiu);<br>
> +<br>
> + } else {<br>
> + npcm_fiux_set_direct_wr(fiu);<br>
> + }<br>
> +<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static int npcm_fiu_setup(struct spi_device *spi)<br>
> +{<br>
> + struct spi_controller *ctrl = spi->master;<br>
> + struct npcm_fiu_spi *fiu = spi_controller_get_devdata(ctrl);<br>
> + struct npcm_fiu_chip *chip;<br>
> +<br>
> + chip = &fiu->chip[spi->chip_select];<br>
> + chip->fiu = fiu;<br>
> + chip->chipselect = spi->chip_select;<br>
> + chip->clkrate = spi->max_speed_hz;<br>
> +<br>
> + fiu->clkrate = clk_get_rate(fiu->clk);<br>
> +<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static const struct spi_controller_mem_ops npcm_fiu_mem_ops = {<br>
> + .exec_op = npcm_fiu_exec_op,<br>
> + .dirmap_create = npcm_fiu_dirmap_create,<br>
> + .dirmap_read = npcm_fiu_direct_read,<br>
> + .dirmap_write = npcm_fiu_direct_write,<br>
> +};<br>
> +<br>
> +static const struct of_device_id npcm_fiu_dt_ids[] = {<br>
> + { .compatible = "nuvoton,npcm750-fiu", .data = &npxm7xx_fiu_data },<br>
> + { /* sentinel */ }<br>
> +};<br>
> +<br>
> +static int npcm_fiu_probe(struct platform_device *pdev)<br>
> +{<br>
> + const struct fiu_data *fiu_data_match;<br>
> + const struct of_device_id *match;<br>
> + struct device *dev = &pdev->dev;<br>
> + struct spi_controller *ctrl;<br>
> + struct npcm_fiu_spi *fiu;<br>
> + void __iomem *regbase;<br>
> + struct resource *res;<br>
> + int ret;<br>
> + int id;<br>
> +<br>
> + ctrl = spi_alloc_master(dev, sizeof(*fiu));<br>
> + if (!ctrl)<br>
> + return -ENOMEM;<br>
> +<br>
> + fiu = spi_controller_get_devdata(ctrl);<br>
> +<br>
> + match = of_match_device(npcm_fiu_dt_ids, dev);<br>
> + if (!match || !match->data) {<br>
> + dev_err(dev, "No compatible OF match\n");<br>
> + return -ENODEV;<br>
> + }<br>
> +<br>
> + fiu_data_match = match->data;<br>
> + id = of_alias_get_id(dev->of_node, "fiu");<br>
> + if (id < 0 || id >= fiu_data_match->fiu_max) {<br>
> + dev_err(dev, "Invalid platform device id: %d\n", id);<br>
> + return -EINVAL;<br>
> + }<br>
> +<br>
> + fiu->info = &fiu_data_match->npcm_fiu_data_info[id];<br>
> +<br>
> + platform_set_drvdata(pdev, fiu);<br>
> + fiu->dev = dev;<br>
> +<br>
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control");<br>
> + regbase = devm_ioremap_resource(dev, res);<br>
> + if (IS_ERR(regbase))<br>
> + return PTR_ERR(regbase);<br>
> +<br>
> + fiu->regmap = devm_regmap_init_mmio(dev, regbase,<br>
> + &npcm_mtd_regmap_config);<br>
> + if (IS_ERR(fiu->regmap)) {<br>
> + dev_err(dev, "Failed to create regmap\n");<br>
> + return PTR_ERR(fiu->regmap);<br>
> + }<br>
> +<br>
> + fiu->res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM,<br>
> + "memory");<br>
> + fiu->clk = devm_clk_get(dev, NULL);<br>
> + if (IS_ERR(fiu->clk))<br>
> + return PTR_ERR(fiu->clk);<br>
> +<br>
> + fiu->spix_mode = of_property_read_bool(dev->of_node, "spix-mode");<br>
> +<br>
> + platform_set_drvdata(pdev, fiu);<br>
> + clk_prepare_enable(fiu->clk);<br>
> +<br>
> + ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD<br>
> + | SPI_TX_DUAL | SPI_TX_QUAD;<br>
> + ctrl->setup = npcm_fiu_setup;<br>
> + ctrl->bus_num = -1;<br>
> + ctrl->mem_ops = &npcm_fiu_mem_ops;<br>
> + ctrl->num_chipselect = fiu->info->max_cs;<br>
> + ctrl->dev.of_node = dev->of_node;<br>
> +<br>
> + ret = devm_spi_register_master(dev, ctrl);<br>
> + if (ret)<br>
> + return ret;<br>
> +<br>
> + dev_info(dev, "NPCM %s probe succeed\n", fiu->info->name);<br>
> +<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static int npcm_fiu_remove(struct platform_device *pdev)<br>
> +{<br>
> + struct npcm_fiu_spi *fiu = platform_get_drvdata(pdev);<br>
> +<br>
> + clk_disable_unprepare(fiu->clk);<br>
> + return 0;<br>
> +}<br>
> +<br>
> +MODULE_DEVICE_TABLE(of, npcm_fiu_dt_ids);<br>
> +<br>
> +static struct platform_driver npcm_fiu_driver = {<br>
> + .driver = {<br>
> + .name = "NPCM-FIU",<br>
> + .bus = &platform_bus_type,<br>
> + .of_match_table = npcm_fiu_dt_ids,<br>
> + },<br>
> + .probe = npcm_fiu_probe,<br>
> + .remove = npcm_fiu_remove,<br>
> +};<br>
> +module_platform_driver(npcm_fiu_driver);<br>
> +<br>
> +MODULE_DESCRIPTION("Nuvoton FLASH Interface Unit SPI Controller Driver");<br>
> +MODULE_AUTHOR("Tomer Maimon <<a href="mailto:tomer.maimon@nuvoton.com" target="_blank">tomer.maimon@nuvoton.com</a>>");<br>
> +MODULE_LICENSE("GPL v2");<br>
> --<br>
> 2.18.0<br>
><br>
</blockquote></div></div>