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<blockquote type="cite" style="margin: 5px 5px; padding-left: 10px; border-left: thin solid #1abc9c;">Why should the aspeed_gates match with SoC default? All clocks will be<br />
set newly according to the dts setting at kernel booting time or at<br />
module probing time.<br />
<br />
Jae</blockquote>
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<div>Sorry, I misunderstand the aspeed_gates purpose. Ignore my question and drop the patch.<br /></div>
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Thanks,
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<div>Samuel Jiang</div>
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<div name="messageReplySection" style="font-size: 14px; font-family: -apple-system, BlinkMacSystemFont, sans-serif;">On Dec 5, 2018, 11:01 PM +0800, Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>, wrote:<br />
<blockquote type="cite" style="margin: 5px 5px; padding-left: 10px; border-left: thin solid #1abc9c;">On 12/5/2018 12:45 AM, Samuel Jiang wrote:<br />
<blockquote type="cite" style="margin: 5px 5px; padding-left: 10px; border-left: thin solid #e67e22;">Hi Ryan,<br />
<br />
I want to confirm the register default set of LCLK is running or stop<br />
for Aspped SoC?<br />
<br />
Hi Jae,<br />
I want to confirm that does the aspeed_gates is set for matching with<br />
the SoC default clock setting?<br />
<br /></blockquote>
<br />
Why should the aspeed_gates match with SoC default? All clocks will be<br />
set newly according to the dts setting at kernel booting time or at<br />
module probing time.<br />
<br />
Jae<br />
<br />
<blockquote type="cite" style="margin: 5px 5px; padding-left: 10px; border-left: thin solid #e67e22;">I need to these things information for joining the discussion to assist<br />
patch to send upstream.<br />
<br />
Thanks,<br />
<br />
Samuel Jiang<br />
<br />
On Dec 4, 2018, 2:17 PM +0800, Ryan Chen , wrote:<br />
<blockquote type="cite" style="margin: 5px 5px; padding-left: 10px; border-left: thin solid #3498db;">Hello Jae,<br />
ASPEED LPC IP HW block have serval clk input.<br />
Most important is LCLK is come from LPC Host.<br />
The others is not controllable by register.<br />
Ryan<br />
<br />
-----Original Message-----<br />
From: Vijay Khemka [mailto:vijaykhemka@fb.com]<br />
Sent: Tuesday, December 4, 2018 3:38 AM<br />
To: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>; Samuel Jiang<br />
<chyishian.jiang@gmail.com>; qianlihu <wangzhiqiang8906@gmail.com>;<br />
Gary Hsu <gary_hsu@aspeedtech.com>; Ryan Chen <ryan_chen@aspeedtech.com><br />
Cc: openbmc@lists.ozlabs.org<br />
Subject: Re: [HELP] ipmi-kcs didn't work<br />
<br />
<br />
<br />
On 12/3/18, 7:54 AM, "Jae Hyun Yoo" <jae.hyun.yoo@linux.intel.com> wrote:<br />
<br />
On 12/1/2018 8:29 AM, Samuel Jiang wrote:<br />
<blockquote type="cite" style="margin: 5px 5px; padding-left: 10px; border-left: thin solid #d35400;">Apologize for sending out no content mail first.<br />
<br />
Jae,<br />
The aspeed_gates in clk-aspeed.c perhaps as todo suggest asking Aspeed<br />
the actual parent data for check initializing?<br />
<br /></blockquote>
<br />
Yes, that makes sense.<br />
<br />
Hi Gary and Ryan,<br />
<br />
Can you please tell us what is the actual parent clock source of LPC IP?<br />
I mean the operational clock of LPC IP hardware block, not the interface<br />
clock.<br />
<br />
Thanks,<br />
Jae<br />
<br />
<blockquote type="cite" style="margin: 5px 5px; padding-left: 10px; border-left: thin solid #d35400;">Vijay,<br />
I traced lpc-ctrl module, it seems direct update the same<br />
ASPEED_CLK_GATE_LCLK register map bit to enable. If parent data is<br />
disabled, it could enable in dts.<br />
The device tree detail, I reference it from aspeed-g5.dtsi. Hope it<br />
could help you for work.<br />
<br />
Thanks,<br />
<br />
Samuel Jiang<br /></blockquote>
<br />
Samual/Jay,<br />
In my case if I don't initialize LPC clock in driver, Bios on host<br />
side wait and doesn't boot.<br />
I don't understand here what is holding Bios here but by initializing<br />
this LPC clock let bios boot.<br />
<br />
Regards<br />
-Vijay<br />
<br /></blockquote>
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