<div dir="ltr"><div>Thanks for sending the patch Andrew. I think it's a viable solution since linux upstream didn't like the idea of misc controls.</div><div><br></div>My feature request would be that we add config options for selectively turning these features on/off. For example, we actually use LPC2AHB and PCIe2AHB downstream for host-BMC mailbox typed transfers.. It would be nice if we could take this patch and define the flags to enable what we needed.</div><br><div class="gmail_quote"><div dir="ltr">On Mon, Jul 23, 2018 at 8:03 AM Andrew Jeffery <<a href="mailto:andrew@aj.id.au" target="_blank">andrew@aj.id.au</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Adjust board_init() to disable hardware features that we don't need<br>
available during normal BMC operation.<br>
<br>
Signed-off-by: Andrew Jeffery <<a href="mailto:andrew@aj.id.au" target="_blank">andrew@aj.id.au</a>><br>
---<br>
arch/arm/include/asm/arch-aspeed/regs-lpc.h | 29 +++++++++++++++<br>
arch/arm/include/asm/arch-aspeed/regs-scu.h | 8 +++-<br>
arch/arm/include/asm/arch-aspeed/regs-sdmc.h | 4 ++<br>
board/aspeed/ast-g4/ast-g4.c | 33 ++++++++++++++++-<br>
board/aspeed/ast-g5/ast-g5.c | 39 +++++++++++++++++++-<br>
5 files changed, 110 insertions(+), 3 deletions(-)<br>
create mode 100644 arch/arm/include/asm/arch-aspeed/regs-lpc.h<br>
<br>
diff --git a/arch/arm/include/asm/arch-aspeed/regs-lpc.h b/arch/arm/include/asm/arch-aspeed/regs-lpc.h<br>
new file mode 100644<br>
index 000000000000..b0162ae4f37c<br>
--- /dev/null<br>
+++ b/arch/arm/include/asm/arch-aspeed/regs-lpc.h<br>
@@ -0,0 +1,29 @@<br>
+/* arch/arm/mach-aspeed/include/mach/regs-sdmc.h<br>
+ *<br>
+ * Copyright (C) 2018 IBM Corp<br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License version 2 as<br>
+ * published by the Free Software Foundation.<br>
+ *<br>
+ * History :<br>
+ * 1. 2018/07/23 Andrew Jeffery Create<br>
+ *<br>
+ ******************************************************************************/<br>
+#ifndef __AST_REGS_LPC_H<br>
+#define __AST_REGS_LPC_H<br>
+<br>
+/*<br>
+ * Register for LPC<br>
+ */<br>
+<br>
+#define AST_LPC_HICR5 0x80<br>
+#define AST_LPC_HICRB 0x100<br>
+<br>
+/* AST_LPC_HICR5 : 0x80 Host Interface Control Register 5 */<br>
+#define LPC_HICR5_ENFWH (0x1 << 10)<br>
+<br>
+/* AST_LPC_HICRB : 0x100 Host Interface Control Register B */<br>
+#define LPC_HICRB_ILPC2AHB (0x1 << 6)<br>
+<br>
+#endif<br>
diff --git a/arch/arm/include/asm/arch-aspeed/regs-scu.h b/arch/arm/include/asm/arch-aspeed/regs-scu.h<br>
index b714fa92341d..c9b91795d1aa 100644<br>
--- a/arch/arm/include/asm/arch-aspeed/regs-scu.h<br>
+++ b/arch/arm/include/asm/arch-aspeed/regs-scu.h<br>
@@ -466,6 +466,7 @@<br>
#define SCU_MISC_JTAG__M_TO_PCIE_EN (0x1 << 14)<br>
#define SCU_MISC_VUART_TO_CTRL (0x1 << 13)<br>
#define SCU_MISC_DIV13_EN (0x1 << 12)<br>
+#define SCU_MISC_DEBUG_UART (0x1 << 10)<br>
#define SCU_MISC_Y_CLK_INVERT (0x1 << 11)<br>
#define SCU_MISC_OUT_DELAY (0x1 << 9)<br>
#define SCU_MISC_PCI_TO_AHB_DIS (0x1 << 8)<br>
@@ -548,6 +549,7 @@<br>
/* AST_SCU_VGA_SCRATCH7 0x6c - VGA Scratch register */<br>
<br>
/* AST_SCU_HW_STRAP1 0x70 - hardware strapping register */<br>
+#define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20)<br>
#ifdef AST_SOC_G5<br>
<br>
#define CLK_25M_IN (0x1 << 23)<br>
@@ -593,7 +595,6 @@<br>
<br>
#define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22)<br>
#define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21)<br>
-#define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20)<br>
#define SCU_HW_STRAP_ACPI_DIS (0x1 << 19)<br>
<br>
/* bit 23, 18 [1,0] */<br>
@@ -940,6 +941,11 @@<br>
<br>
/* AST_SCU_UART24_REF 0x160 - Generate UART 24Mhz Ref from H-PLL when CLKIN is 25Mhz */<br>
/* AST_SCU_PCIE_CONFIG_SET 0x180 - PCI-E Configuration Setting Control Register */<br>
+#define SCU_PCIE_CONFIG_SET_BMC_DMA (0x1 << 14)<br>
+#define SCU_PCIE_CONFIG_SET_BMC_MMIO (0x1 << 9)<br>
+#define SCU_PCIE_CONFIG_SET_BMC_EN (0x1 << 8)<br>
+#define SCU_PCIE_CONFIG_SET_VGA_MMIO (0x1 << 1)<br>
+<br>
/* AST_SCU_BMC_MMIO_DEC 0x184 - BMC MMIO Decode Setting Register */<br>
/* AST_SCU_DEC_AREA1 0x188 - 1st relocated controller decode area location */<br>
/* AST_SCU_DEC_AREA2 0x18C - 2nd relocated controller decode area location */<br>
diff --git a/arch/arm/include/asm/arch-aspeed/regs-sdmc.h b/arch/arm/include/asm/arch-aspeed/regs-sdmc.h<br>
index 2cc26d29aa9e..3b516ecccdde 100644<br>
--- a/arch/arm/include/asm/arch-aspeed/regs-sdmc.h<br>
+++ b/arch/arm/include/asm/arch-aspeed/regs-sdmc.h<br>
@@ -18,6 +18,7 @@<br>
*/<br>
#define AST_SDMC_PROTECT 0x00 /* protection key register */<br>
#define AST_SDMC_CONFIG 0x04 /* Configuration register */<br>
+#define AST_SDMC_GFX_PROT 0x08 /* Graphics protection register */<br>
<br>
/* AST_SDMC_PROTECT: 0x00 - protection key register */<br>
#define SDMC_PROTECT_UNLOCK 0xFC600309<br>
@@ -29,4 +30,7 @@<br>
#define SDMC_CONFIG_CACHE_EN (0x1 << 10)<br>
#define SDMC_CONFIG_EEC_EN (0x1 << 7)<br>
<br>
+/* AST_SDMC_GFX_PROT : 0x08 - Graphics protection register */<br>
+#define SDMC_GFX_PROT_XDMA (0x1 << 16)<br>
+<br>
#endif<br>
diff --git a/board/aspeed/ast-g4/ast-g4.c b/board/aspeed/ast-g4/ast-g4.c<br>
index 656495307b03..eda087fa5c17 100644<br>
--- a/board/aspeed/ast-g4/ast-g4.c<br>
+++ b/board/aspeed/ast-g4/ast-g4.c<br>
@@ -1,6 +1,6 @@<br>
/*<br>
* (C) Copyright 2002 Ryan Chen<br>
- * Copyright 2016 IBM Corporation<br>
+ * Copyright 2016,2018 IBM Corporation<br>
*<br>
* SPDX-License-Identifier: GPL-2.0+<br>
*/<br>
@@ -12,13 +12,44 @@<br>
#include <asm/arch/ast-sdmc.h><br>
#include <asm/arch/ast_scu.h><br>
#include <asm/arch/regs-ahbc.h><br>
+#include <asm/arch/regs-lpc.h><br>
#include <asm/arch/regs-scu.h><br>
+#include <asm/arch/regs-sdmc.h><br>
#include <asm/io.h><br>
<br>
DECLARE_GLOBAL_DATA_PTR;<br>
<br>
int board_init(void)<br>
{<br>
+ u32 val;<br>
+<br>
+ /* iLPC2AHB */<br>
+ val = readl(AST_SCU_BASE + AST_SCU_HW_STRAP1);<br>
+ val |= SCU_HW_STRAP_LPC_DEC_SUPER_IO;<br>
+ writel(val, AST_SCU_BASE + AST_SCU_HW_STRAP1);<br>
+<br>
+ val = readl(AST_LPC_BASE + AST_LPC_HICRB);<br>
+ val |= LPC_HICRB_ILPC2AHB;<br>
+ writel(val, AST_LPC_BASE + AST_LPC_HICRB);<br>
+<br>
+ /* P2A, PCIe BMC */<br>
+ val = readl(AST_SCU_BASE + AST_SCU_PCIE_CONFIG_SET);<br>
+ val &= ~(SCU_PCIE_CONFIG_SET_BMC_DMA<br>
+ | SCU_PCIE_CONFIG_SET_BMC_MMIO<br>
+ | SCU_PCIE_CONFIG_SET_BMC_EN<br>
+ | SCU_PCIE_CONFIG_SET_VGA_MMIO);<br>
+ writel(val, AST_SCU_BASE + AST_SCU_PCIE_CONFIG_SET);<br>
+<br>
+ /* X-DMA */<br>
+ val = readl(AST_SDMC_BASE + AST_SDMC_GFX_PROT);<br>
+ val |= SDMC_GFX_PROT_XDMA;<br>
+ writel(val, AST_SDMC_BASE + AST_SDMC_GFX_PROT);<br>
+<br>
+ /* LPC2AHB */<br>
+ val = readl(AST_LPC_BASE + AST_LPC_HICR5);<br>
+ val &= ~LPC_HICR5_ENFWH;<br>
+ writel(val, AST_LPC_BASE + AST_LPC_HICR5);<br>
+<br>
/* address of boot parameters */<br>
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;<br>
gd->flags = 0;<br>
diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c<br>
index e67a4bf8b2b4..e8827524e3b2 100644<br>
--- a/board/aspeed/ast-g5/ast-g5.c<br>
+++ b/board/aspeed/ast-g5/ast-g5.c<br>
@@ -1,5 +1,5 @@<br>
/*<br>
- * Copyright 2016 IBM Corporation<br>
+ * Copyright 2016,2018 IBM Corporation<br>
*<br>
* This program is free software; you can redistribute it and/or<br>
* modify it under the terms of the GNU General Public License<br>
@@ -12,12 +12,49 @@<br>
<br>
#include <asm/arch/ast_scu.h><br>
#include <asm/arch/ast-sdmc.h><br>
+#include <asm/arch/regs-lpc.h><br>
+#include <asm/arch/regs-scu.h><br>
+#include <asm/arch/regs-sdmc.h><br>
#include <asm/io.h><br>
<br>
DECLARE_GLOBAL_DATA_PTR;<br>
<br>
int board_init(void)<br>
{<br>
+ u32 val;<br>
+<br>
+ /* iLPC2AHB */<br>
+ val = readl(AST_SCU_BASE + AST_SCU_HW_STRAP1);<br>
+ val |= SCU_HW_STRAP_LPC_DEC_SUPER_IO;<br>
+ writel(val, AST_SCU_BASE + AST_SCU_HW_STRAP1);<br>
+<br>
+ val = readl(AST_LPC_BASE + AST_LPC_HICRB);<br>
+ val |= LPC_HICRB_ILPC2AHB;<br>
+ writel(val, AST_LPC_BASE + AST_LPC_HICRB);<br>
+<br>
+ /* P2A, PCIe BMC */<br>
+ val = readl(AST_SCU_BASE + AST_SCU_PCIE_CONFIG_SET);<br>
+ val &= ~(SCU_PCIE_CONFIG_SET_BMC_DMA<br>
+ | SCU_PCIE_CONFIG_SET_BMC_MMIO<br>
+ | SCU_PCIE_CONFIG_SET_BMC_EN<br>
+ | SCU_PCIE_CONFIG_SET_VGA_MMIO);<br>
+ writel(val, AST_SCU_BASE + AST_SCU_PCIE_CONFIG_SET);<br>
+<br>
+ /* Debug UART */<br>
+ val = readl(AST_SCU_BASE + AST_SCU_MISC1_CTRL);<br>
+ val |= SCU_MISC_DEBUG_UART;<br>
+ writel(val, AST_SCU_BASE + AST_SCU_MISC1_CTRL);<br>
+<br>
+ /* X-DMA */<br>
+ val = readl(AST_SDMC_BASE + AST_SDMC_GFX_PROT);<br>
+ val |= SDMC_GFX_PROT_XDMA;<br>
+ writel(val, AST_SDMC_BASE + AST_SDMC_GFX_PROT);<br>
+<br>
+ /* LPC2AHB */<br>
+ val = readl(AST_LPC_BASE + AST_LPC_HICR5);<br>
+ val &= ~LPC_HICR5_ENFWH;<br>
+ writel(val, AST_LPC_BASE + AST_LPC_HICR5);<br>
+<br>
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;<br>
gd->flags = 0;<br>
<br>
-- <br>
2.17.1<br>
<br>
</blockquote></div><br clear="all"><div><br></div>-- <br><div dir="ltr" class="m_6379003548251518587m_-7992730932912437700gmail_signature" data-smartmail="gmail_signature"><div dir="ltr">Regards,<div>Kun</div></div></div>