<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Oct 27, 2016 at 4:40 PM, Jaghathiswari Rankappagounder Natarajan <span dir="ltr"><<a href="mailto:jaghu@google.com" target="_blank">jaghu@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Signed-off-by: Jaghathiswari Rankappagounder Natarajan <<a href="mailto:jaghu@google.com">jaghu@google.com</a>><br>
---<br>
 arch/arm/boot/dts/aspeed-bmc-<wbr>opp-zaius.dts | 63 ++++++++++++++++++++++++++++++<br>
 1 file changed, 63 insertions(+)<br>
<br>
diff --git a/arch/arm/boot/dts/aspeed-<wbr>bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-<wbr>bmc-opp-zaius.dts<br>
index eef045b..82a12dc 100644<br>
--- a/arch/arm/boot/dts/aspeed-<wbr>bmc-opp-zaius.dts<br>
+++ b/arch/arm/boot/dts/aspeed-<wbr>bmc-opp-zaius.dts<br>
@@ -83,6 +83,69 @@<br>
                        gpios = <&gpio ASPEED_GPIO(H, 7) GPIO_ACTIVE_LOW>;<br>
                };<br>
        };<br>
+<br>
+       pwm_controller {<br>
+               #address-cells = <1>;<br>
+               #size-cells = <1>;<br>
+               reg = <0x1E786000 0x78>;<br>
+               compatible = "aspeed-pwm-controller";<br>
+               clock_enable = /bits/ 8 <0x01>;<br>
+               clock_source = /bits/ 8 <0x00>;<br>
+               typem_pwm_clock = <5 0 95>;<br>
+       };<br>
+<br>
+       pwm0 {<br>
+                       #address-cells = <1>;<br>
+                       #size-cells = <1>;<br>
+                       reg = <0x1E786000 0x78>;<br>
+                       compatible = "aspeed-pwm-dev";<br>
+                       pinctrl-names = "default";<br>
+                       pinctrl-0 = <&pinctrl_pwm0_default>;<br>
+                       pwm_channel_enable = /bits/ 8 <0x00>;<br>
+                       pwm_type = /bits/ 8 <0x00>;<br>
+                       rising = /bits/ 8 <0x00>;<br>
+                       falling = /bits/ 8 <0x00>;<br>
+       };<br>
+<br></blockquote><div><br></div><div>As Andrew mentioned in a reply to your cover letter, please explain the structure of the hardware and the drivers.  I see that you are repeating the register address range in each pwmX entry.  That should go away if you make the pwmX entries children of the pwm_controller entry.  I think you can use address cell in the children to indicate the PWM channel # and let pwm_controller map that back to the correct physical address.</div><div> <br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+       pwm1 {<br>
+                       #address-cells = <1>;<br>
+                       #size-cells = <1>;<br>
+                       reg = <0x1E786000 0x78>;<br>
+                       compatible = "aspeed-pwm-dev";<br>
+                       pinctrl-names = "default";<br>
+                       pinctrl-0 = <&pinctrl_pwm1_default>;<br>
+                       pwm_channel_enable = /bits/ 8 <0x01>;<br>
+                       pwm_type = /bits/ 8 <0x00>;<br>
+                       rising = /bits/ 8 <0x00>;<br>
+                       falling = /bits/ 8 <0x00>;<br>
+       };<br>
+<br>
+       pwm2 {<br>
+                       #address-cells = <1>;<br>
+                       #size-cells = <1>;<br>
+                       reg = <0x1E786000 0x78>;<br>
+                       compatible = "aspeed-pwm-dev";<br>
+                       pinctrl-names = "default";<br>
+                       pinctrl-0 = <&pinctrl_pwm2_default>;<br>
+                       pwm_channel_enable = /bits/ 8 <0x02>;<br>
+                       pwm_type = /bits/ 8 <0x00>;<br>
+                       rising = /bits/ 8 <0x00>;<br>
+                       falling = /bits/ 8 <0x00>;<br>
+       };<br>
+<br>
+       pwm3 {<br>
+                       #address-cells = <1>;<br>
+                       #size-cells = <1>;<br>
+                       reg = <0x1E786000 0x78>;<br>
+                       compatible = "aspeed-pwm-dev";<br>
+                       pinctrl-names = "default";<br>
+                       pinctrl-0 = <&pinctrl_pwm3_default>;<br>
+                       pwm_channel_enable = /bits/ 8 <0x03>;<br>
+                       pwm_type = /bits/ 8 <0x00>;<br>
+                       rising = /bits/ 8 <0x00>;<br>
+                       falling = /bits/ 8 <0x00>;<br>
+       };<br>
+<br>
 };<br>
<br>
 &uart5 {<br>
--<br>
2.8.0.rc3.226.g39d4020<br>
<br>
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</blockquote></div><br></div></div>