<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Sep 28, 2016 at 6:27 PM, Joel Stanley <span dir="ltr"><<a href="mailto:joel@jms.id.au" target="_blank">joel@jms.id.au</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">On Wed, Sep 28, 2016 at 3:13 AM, <<a href="mailto:maxims@google.com">maxims@google.com</a>> wrote:<br>
> From: Maxim Sloyko <<a href="mailto:maxims@google.com">maxims@google.com</a>><br>
><br>
> The driver is very limited: only single master mode is supported<br>
> and only byte-by-byte synchronous reads and writes are supported,<br>
> no Pool Buffers or DMA.<br>
<br>
</span>Your subject string mentions g5, but I think this is a generic Aspeed<br>
i2c driver that will work on the g4 platforms as well.<br></blockquote><div><br></div><div>I changed it to say g5/g4, but I haven't actually tested it on ast2400.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div><div class="h5"><br>
> ---<br>
> drivers/i2c/Kconfig | 6 +<br>
> drivers/i2c/Makefile | 1 +<br>
> drivers/i2c/ast_i2c.c | 306 ++++++++++++++++++++++++++++++<wbr>++++++++++++++++++++<br>
> drivers/i2c/ast_i2c.h | 155 +++++++++++++++++++++++++<br>
> 4 files changed, 468 insertions(+)<br>
> create mode 100644 drivers/i2c/ast_i2c.c<br>
> create mode 100644 drivers/i2c/ast_i2c.h<br>
><br>
> diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig<br>
> index 9324c6c..6501e91 100644<br>
> --- a/drivers/i2c/Kconfig<br>
> +++ b/drivers/i2c/Kconfig<br>
> @@ -65,6 +65,12 @@ config SYS_I2C_CADENCE<br>
> Say yes here to select Cadence I2C Host Controller. This controller is<br>
> e.g. used by Xilinx Zynq.<br>
><br>
> +config SYS_I2C_AST<br>
> + tristate "Aspeed I2C Controller"<br>
> + depends on DM_I2C<br>
> + help<br>
> + Say yes here to select Aspeed I2C Host Controller.<br>
> +<br>
> config SYS_I2C_INTEL<br>
> bool "Intel I2C/SMBUS driver"<br>
> depends on DM_I2C<br>
> diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile<br>
> index 167424d..89e046e 100644<br>
> --- a/drivers/i2c/Makefile<br>
> +++ b/drivers/i2c/Makefile<br>
> @@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o<br>
> obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o<br>
> obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o<br>
> obj-$(CONFIG_SYS_I2C) += i2c_core.o<br>
> +obj-$(CONFIG_SYS_I2C_AST) += ast_i2c.o<br>
> obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o<br>
> obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o<br>
> obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o<br>
> diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c<br>
> new file mode 100644<br>
> index 0000000..c7bc199<br>
> --- /dev/null<br>
> +++ b/drivers/i2c/ast_i2c.c<br>
> @@ -0,0 +1,306 @@<br>
> +/*<br>
> + * Copyright (C) 2016 Google, Inc<br>
<br>
</div></div>The driver looks to be copied at least in part from the kernel one.<br></blockquote><div><br></div><div>Fixed.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div><div class="h5"><br>
> + *<br>
> + * SPDX-License-Identifier: GPL-2.0+<br>
> + */<br>
> +<br>
> +#include <common.h><br>
> +#include <dm.h><br>
> +#include <fdtdec.h><br>
> +#include <i2c.h><br>
> +<br>
> +#include <asm/arch/ast_scu.h><br>
> +#include <asm/arch/regs-scu.h><br>
> +#include <asm/io.h><br>
> +<br>
> +#include "ast_i2c.h"<br>
> +<br>
> +#define I2C_TIMEOUT_US (100000)<br>
> +#define I2C_SLEEP_STEP (20)<br>
> +#define EI2C_TIMEOUT (1001)<br>
> +<br>
> +DECLARE_GLOBAL_DATA_PTR;<br>
> +<br>
> +struct ast_i2c {<br>
> + u32 id;<br>
> + struct ast_i2c_regs *regs;<br>
> + int speed;<br>
> +};<br>
> +<br>
> +#define RETURN_IF_ERROR(expr) do {\<br>
> + int err = (expr);\<br>
> + if (err < 0) {\<br>
> + return err;\<br>
> + }\<br>
> +} while (0)<br>
<br>
</div></div>u-boot upstream does not use macros like this.<br></blockquote><div><br></div><div>Fixed.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<span class=""><br>
> +<br>
> +static u32 __get_clk_reg_val(u32 divider_ratio)<br>
<br>
</span>Why the __ prefix? I think you should remove it.<br></blockquote><div><br></div><div>Removed.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<span class=""><br>
> +{<br>
> + unsigned int inc = 0, div;<br>
> + u32 scl_low, scl_high, data;<br>
> +<br>
> + for (div = 0; divider_ratio >= 16; div++) {<br>
> + inc |= (divider_ratio & 1);<br>
> + divider_ratio >>= 1;<br>
> + }<br>
> + divider_ratio += inc;<br>
> + scl_low = (divider_ratio >> 1) - 1;<br>
> + scl_high = divider_ratio - scl_low - 2;<br>
> + data = 0x77700300 | (scl_high << 16) | (scl_low << 12) | div;<br>
> + return data;<br>
> +}<br>
> +<br>
> +static inline void __ast_i2c_clear_interrupts(<wbr>struct ast_i2c_regs *i2c_base)<br>
<br>
</span>Remove the __ prefix.<br>
<span class=""><br>
> +{<br>
> + writel(~0, &i2c_base->isr);<br>
> +}<br>
> +<br>
> +static int __ast_i2c_init_bus(struct ast_i2c *i2c_bus)<br>
<br>
</span>Remove the __ prefix.<br>
<span class=""><br>
> +{<br>
> + /* Reset device */<br>
> + writel(0, &i2c_bus->regs->fcr);<br>
> + /* Enable Master Mode. Assuming single-master. */<br>
> + debug("Enable Master for %p\n", i2c_bus->regs);<br>
> + setbits_le32(&i2c_bus->regs-><wbr>fcr,<br>
> + AST_I2CD_MASTER_EN<br>
> + | AST_I2CD_M_SDA_LOCK_EN<br>
> + | AST_I2CD_MULTI_MASTER_DIS | AST_I2CD_M_SCL_DRIVE_EN);<br>
> + debug("FCR: %p\n", &i2c_bus->regs->fcr);<br>
> + /* Enable Interrupts */<br>
> + writel(AST_I2CD_INTR_TX_ACK<br>
> + | AST_I2CD_INTR_TX_NAK<br>
> + | AST_I2CD_INTR_RX_DONE<br>
> + | AST_I2CD_INTR_BUS_RECOVER_DONE<br>
> + | AST_I2CD_INTR_NORMAL_STOP<br>
> + | AST_I2CD_INTR_ABNORMAL, &i2c_bus->regs->icr);<br>
> + return 0;<br>
<br>
</span>Change the return type to void if you're not using it.<br></blockquote><div><br></div><div>Done.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<span class=""><br>
> +}<br>
> +<br>
> +static int ast_i2c_probe(struct udevice *dev)<br>
> +{<br>
> + struct ast_i2c *i2c_bus = dev_get_priv(dev);<br>
> +<br>
> + debug("Enabling I2C%u \n", dev->seq);<br>
> + ast_scu_enable_i2c(dev->seq);<br>
> +<br>
> + i2c_bus->id = dev->seq;<br>
> + struct ast_i2c_regs *i2c_base =<br>
> + (struct ast_i2c_regs *)dev_get_addr(dev);<br>
> + i2c_bus->regs = i2c_base;<br>
> +<br>
> + return __ast_i2c_init_bus(i2c_bus);<br>
<br>
</span>__ast_i2c_init_bus always returns 0, so this can return void.<br></blockquote><div><br></div><div>It's part of driver's API, so has a fixed signature.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div><div class="h5"><br>
> +}<br>
> +<br>
> +static inline int __ast_i2c_wait_isr(struct ast_i2c_regs *i2c_base, u32 flag)<br>
> +{<br>
> + int timeout = I2C_TIMEOUT_US;<br>
> + while (!(readl(&i2c_base->isr) & flag) && timeout > 0) {<br>
> + udelay(I2C_SLEEP_STEP);<br>
> + timeout -= I2C_SLEEP_STEP;<br>
> + }<br>
> +<br>
> + __ast_i2c_clear_interrupts(<wbr>i2c_base);<br>
> + if (timeout <= 0)<br>
> + return -EI2C_TIMEOUT;<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static inline int __ast_i2c_send_stop(struct ast_i2c_regs *i2c_base)<br>
> +{<br>
> + writel(AST_I2CD_M_STOP_CMD, &i2c_base->csr);<br>
> + RETURN_IF_ERROR(__ast_i2c_<wbr>wait_isr<br>
> + (i2c_base, AST_I2CD_INTR_NORMAL_STOP));<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static inline int __ast_i2c_wait_tx(struct ast_i2c_regs *i2c_base)<br>
> +{<br>
> + int timeout = I2C_TIMEOUT_US;<br>
> + u32 flag = AST_I2CD_INTR_TX_ACK | AST_I2CD_INTR_TX_NAK;<br>
> + u32 status = readl(&i2c_base->isr) & flag;<br>
> + while (!status && timeout > 0) {<br>
> + status = readl(&i2c_base->isr) & flag;<br>
> + udelay(I2C_SLEEP_STEP);<br>
> + timeout -= I2C_SLEEP_STEP;<br>
> + }<br>
> +<br>
> + int ret = 0;<br>
> + if (status == AST_I2CD_INTR_TX_NAK) {<br>
> + ret = -EREMOTEIO;<br>
> + }<br>
> +<br>
> + if (timeout <= 0) {<br>
> + ret = -EI2C_TIMEOUT;<br>
> + }<br>
> +<br>
> + __ast_i2c_clear_interrupts(<wbr>i2c_base);<br>
> + return ret;<br>
> +}<br>
> +<br>
> +static inline int __ast_i2c_start_txn(struct ast_i2c_regs *i2c_base, u8 devaddr)<br>
<br>
</div></div>Remove the __ prefix.<br>
<br>
What's the "n" mean after tx? Or does txn mean transaction?<br></blockquote><div><br></div><div>Yes, this means transaction.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<span class=""><br>
> +{<br>
> + /* Start and Send Device Address */<br>
> + writel(devaddr, &i2c_base->trbbr);<br>
> + writel(AST_I2CD_M_START_CMD | AST_I2CD_M_TX_CMD, &i2c_base->csr);<br>
> + RETURN_IF_ERROR(__ast_i2c_<wbr>wait_tx(i2c_base));<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static int __ast_i2c_read_data(struct ast_i2c *i2c_bus, u8 chip, u8 *buffer,<br>
> + int len)<br>
<br>
</span>Remove the __ prefix.<br>
<br>
What is chip in this case? I think it's the i2c slave's address. Make<br>
that clearer please.<br></blockquote><div><br></div><div>Main drivers/i2c.h file uses names chip and chip_address for this purpose, so I just picked one.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
len can be a size_t.<br>
<span class=""><br>
> +{<br>
> + int i2c_error = 0;<br>
<br>
</span>No need to initialise this here.<br>
<span class=""><br>
> + struct ast_i2c_regs *i2c_base = i2c_bus->regs;<br>
> +<br>
> + i2c_error = __ast_i2c_start_txn(i2c_base, (chip << 1) | I2C_M_RD);<br>
<br>
</span>Test for the error and return here to make it clear that no further<br>
processing occurs.<br>
<span class=""><br>
> +<br>
> + if (!i2c_error) {<br>
> + u32 i2c_cmd = AST_I2CD_M_RX_CMD;<br>
> + for (; len > 0; len--, buffer++) {<br>
> + if (len == 1) {<br>
> + i2c_cmd |= AST_I2CD_M_S_RX_CMD_LAST;<br>
> + }<br>
> + writel(i2c_cmd, &i2c_base->csr);<br>
> + RETURN_IF_ERROR(__ast_i2c_<wbr>wait_isr<br>
> + (i2c_base, AST_I2CD_INTR_RX_DONE));<br>
> + *buffer = AST_I2CD_RX_DATA_BUF_GET(<wbr>readl(&i2c_base->trbbr));<br>
> + }<br>
> + __ast_i2c_clear_interrupts(<wbr>i2c_base);<br>
> + }<br>
> + RETURN_IF_ERROR(__ast_i2c_<wbr>send_stop(i2c_base));<br>
<br>
</span>I don't think your RETURN_IF_ERROR macro does anything for readability<br>
here. You're going to return regardless, so do:<br>
<br>
return __ast_i2c_send_stop(i2c_base);<br>
<span class=""><br>
> +<br>
> + return i2c_error;<br>
> +}<br>
> +<br>
> +static int __ast_i2c_write_data(struct ast_i2c *i2c_bus, u8 chip, u8 *buffer,<br>
> + int len)<br>
<br>
</span>Similar comments as for read_data above.<br>
<div><div class="h5"><br>
> +{<br>
> + int i2c_error = 0;<br>
> + struct ast_i2c_regs *i2c_base = i2c_bus->regs;<br>
> +<br>
> + i2c_error = __ast_i2c_start_txn(i2c_base, (chip << 1));<br>
> + for (; len > 0 && 0 == i2c_error; len--, buffer++) {<br>
> + writel(*buffer, &i2c_base->trbbr);<br>
> + writel(AST_I2CD_M_TX_CMD, &i2c_base->csr);<br>
> + i2c_error = __ast_i2c_wait_tx(i2c_base);<br>
> + }<br>
> + RETURN_IF_ERROR(__ast_i2c_<wbr>send_stop(i2c_base));<br>
> + return i2c_error;<br>
> +}<br>
> +<br>
> +static int ast_i2c_deblock(struct udevice *dev)<br>
> +{<br>
> + struct ast_i2c *i2c_bus = dev_get_priv(dev);<br>
> + struct ast_i2c_regs *i2c_base = i2c_bus->regs;<br>
> +<br>
> + u32 csr = readl(&i2c_base->csr);<br>
> + debug("Bus hung (%x), attempting recovery\n", csr);<br>
> +<br>
> + bool sda_high = csr & AST_I2CD_SDA_LINE_STS;<br>
> + bool scl_high = csr & AST_I2CD_SCL_LINE_STS;<br>
> + if (sda_high && scl_high) {<br>
> + /* Bus is idle, no deblocking needed. */<br>
> + return 0;<br>
> + } else if (sda_high) {<br>
> + /* Send stop command */<br>
> + RETURN_IF_ERROR(__ast_i2c_<wbr>send_stop(i2c_base));<br>
> + } else if (scl_high) {<br>
> + /* Possibly stuck slave */<br>
> + writel(AST_I2CD_BUS_RECOVER_<wbr>CMD, &i2c_base->csr);<br>
> + RETURN_IF_ERROR(__ast_i2c_<wbr>wait_isr<br>
> + (i2c_base, AST_I2CD_INTR_BUS_RECOVER_<wbr>DONE));<br>
> + } else {<br>
> + /* Just try to reinit the device. */<br>
> + RETURN_IF_ERROR(__ast_i2c_<wbr>init_bus(i2c_bus));<br>
> + }<br>
> +<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static int ast_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)<br>
> +{<br>
> + struct ast_i2c *i2c_bus = dev_get_priv(dev);<br>
> + int ret;<br>
> +<br>
> + debug("i2c_xfer: %d messages\n", nmsgs);<br>
> + for (; nmsgs > 0; nmsgs--, msg++) {<br>
> + /* TODO: use this for repeated start */<br>
> + bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);<br>
> +<br>
> + if (msg->flags & I2C_M_RD) {<br>
> + debug("i2c_read: chip=0x%x, len=0x%x, flags=0x%x\n",<br>
> + msg->addr, msg->len, msg->flags);<br>
> + ret =<br>
> + __ast_i2c_read_data(i2c_bus, msg->addr, msg->buf,<br>
> + msg->len);<br>
> + } else {<br>
> + debug("i2c_write: chip=0x%x, len=0x%x, flags=0x%x\n",<br>
> + msg->addr, msg->len, msg->flags);<br>
> + ret =<br>
> + __ast_i2c_write_data(i2c_bus, msg->addr, msg->buf,<br>
> + msg->len);<br>
> + }<br>
> + if (ret) {<br>
> + debug("%s: error (%d)\n", __func__, ret);<br>
> + return -EREMOTEIO;<br>
> + }<br>
> + }<br>
> +<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static int ast_i2c_set_speed(struct udevice *dev, unsigned int speed)<br>
> +{<br>
> + debug("Setting speed ofr I2C%d to <%u>\n", dev->seq, speed);<br>
> + if (!speed) {<br>
> + debug("No valid speed specified.\n");<br>
> + return -EINVAL;<br>
> + }<br>
> + struct ast_i2c *i2c_bus = dev_get_priv(dev);<br>
> +<br>
> + i2c_bus->speed = speed;<br>
> + /* TODO: get this from device tree */<br>
> + u32 pclk = ast_get_apbclk();<br>
> + u32 divider = pclk / speed;<br>
> +<br>
> + struct ast_i2c_regs *i2c_base = i2c_bus->regs;<br>
> + if (speed > 400000) {<br>
> + debug("Enabling High Speed\n");<br>
> + setbits_le32(&i2c_base->fcr, AST_I2CD_M_HIGH_SPEED_EN<br>
> + | AST_I2CD_M_SDA_DRIVE_1T_EN<br>
> + | AST_I2CD_SDA_DRIVE_1T_EN);<br>
> + writel(0x3, &i2c_base->cactcr2);<br>
> + writel(__get_clk_reg_val(<wbr>divider), &i2c_base->cactcr1);<br>
> + } else {<br>
> + debug("Enabling Normal Speed\n");<br>
> + writel(__get_clk_reg_val(<wbr>divider), &i2c_base->cactcr1);<br>
> + writel(AST_NO_TIMEOUT_CTRL, &i2c_base->cactcr2);<br>
> + }<br>
> +<br>
> + __ast_i2c_clear_interrupts(<wbr>i2c_base);<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static const struct dm_i2c_ops ast_i2c_ops = {<br>
> + .xfer = ast_i2c_xfer,<br>
> + .set_bus_speed = ast_i2c_set_speed,<br>
> + .deblock = ast_i2c_deblock,<br>
> +};<br>
> +<br>
> +static const struct udevice_id ast_i2c_ids[] = {<br>
> + {.compatible = "aspeed,ast2400-i2c-<wbr>controller",},<br>
> + {.compatible = "aspeed,ast2400-i2c-bus",},<br>
<br>
</div></div>Your subject says g5, but your compatible strings say g4.<br>
<br>
Your probe function doesn't test for which string you're using. Why do<br>
you have both -controller and -bus?<br></blockquote><div><br></div><div>I think this has something to do with how the device tree is processed, but it seems that because i2c buses are specified under a single controller node, if I don't specify compatibility with -controller, it does not match -bus nodes. </div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div><div class="h5"><br>
> + {},<br>
> +};<br>
> +<br>
> +/* Tell GNU Indent to keep this as is: */<br>
> +/* *INDENT-OFF* */<br>
> +U_BOOT_DRIVER(i2c_aspeed) = {<br>
> + .name = "i2c_aspeed",<br>
> + .id = UCLASS_I2C,<br>
> + .of_match = ast_i2c_ids,<br>
> + .probe = ast_i2c_probe,<br>
> + .priv_auto_alloc_size = sizeof(struct ast_i2c),<br>
> + .ops = &ast_i2c_ops,<br>
> +};<br>
> +/* *INDENT-ON* */<br>
> diff --git a/drivers/i2c/ast_i2c.h b/drivers/i2c/ast_i2c.h<br>
> new file mode 100644<br>
> index 0000000..e221b41<br>
> --- /dev/null<br>
> +++ b/drivers/i2c/ast_i2c.h<br>
> @@ -0,0 +1,155 @@<br>
> +/*<br>
> + * Copyright (C) 2016 Google, Inc<br>
> + *<br>
> + * SPDX-License-Identifier: GPL-2.0+<br>
> + */<br>
> +#ifndef __AST_I2C_H_<br>
> +#define __AST_I2C_H_<br>
> +<br>
> +struct ast_i2c_regs {<br>
> + uint32_t fcr;<br>
> + uint32_t cactcr1;<br>
> + uint32_t cactcr2;<br>
> + uint32_t icr;<br>
> + uint32_t isr;<br>
> + uint32_t csr;<br>
> + uint32_t sdar;<br>
> + uint32_t pbcr;<br>
> + uint32_t trbbr;<br>
> +#ifdef CONFIG_TARGET_AST_G5<br>
> + uint32_t dma_mbar;<br>
> + uint32_t dma_tlr;<br>
> +#endif<br>
> +};<br>
> +<br>
> +/* Device Register Definition */<br>
> +/* 0x00 : I2CD Function Control Register */<br>
> +#define AST_I2CD_BUFF_SEL_MASK (0x7 << 20)<br>
> +#define AST_I2CD_BUFF_SEL(x) (x << 20) // page 0 ~ 7<br>
> +#define AST_I2CD_M_SDA_LOCK_EN (0x1 << 16)<br>
> +#define AST_I2CD_MULTI_MASTER_DIS (0x1 << 15)<br>
> +#define AST_I2CD_M_SCL_DRIVE_EN (0x1 << 14)<br>
> +#define AST_I2CD_MSB_STS (0x1 << 9)<br>
> +#define AST_I2CD_SDA_DRIVE_1T_EN (0x1 << 8)<br>
> +#define AST_I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7)<br>
> +#define AST_I2CD_M_HIGH_SPEED_EN (0x1 << 6)<br>
> +#define AST_I2CD_DEF_ADDR_EN (0x1 << 5)<br>
> +#define AST_I2CD_DEF_ALERT_EN (0x1 << 4)<br>
> +#define AST_I2CD_DEF_ARP_EN (0x1 << 3)<br>
> +#define AST_I2CD_DEF_GCALL_EN (0x1 << 2)<br>
> +#define AST_I2CD_SLAVE_EN (0x1 << 1)<br>
> +#define AST_I2CD_MASTER_EN (0x1 )<br>
> +<br>
> +/* 0x04 : I2CD Clock and AC Timing Control Register #1 */<br>
> +#define AST_I2CD_tBUF (0x1 << 28) // 0~7<br>
> +#define AST_I2CD_tHDSTA (0x1 << 24) // 0~7<br>
> +#define AST_I2CD_tACST (0x1 << 20) // 0~7<br>
> +#define AST_I2CD_tCKHIGH (0x1 << 16) // 0~7<br>
> +#define AST_I2CD_tCKLOW (0x1 << 12) // 0~7<br>
> +#define AST_I2CD_tHDDAT (0x1 << 10) // 0~7<br>
> +#define AST_I2CD_CLK_TO_BASE_DIV (0x1 << 8) // 0~3<br>
> +#define AST_I2CD_CLK_BASE_DIV (0x1 ) // 0~0xf<br>
> +<br>
> +/* 0x08 : I2CD Clock and AC Timing Control Register #2 */<br>
> +#define AST_I2CD_tTIMEOUT (0x1 ) // 0~7<br>
> +#define AST_NO_TIMEOUT_CTRL 0x0<br>
> +<br>
> +/* 0x0c : I2CD Interrupt Control Register &<br>
> + * 0x10 : I2CD Interrupt Status Register<br>
> + *<br>
> + * These share bit definitions, so use the same values for the enable &<br>
> + * status bits.<br>
> + */<br>
> +#define AST_I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14)<br>
> +#define AST_I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13)<br>
> +#define AST_I2CD_INTR_SMBUS_ALERT (0x1 << 12)<br>
> +#define AST_I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11)<br>
> +#define AST_I2CD_INTR_SMBUS_DEV_ALERT_<wbr>ADDR (0x1 << 10)<br>
> +#define AST_I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9)<br>
> +#define AST_I2CD_INTR_GCALL_ADDR (0x1 << 8)<br>
> +#define AST_I2CD_INTR_SLAVE_MATCH (0x1 << 7)<br>
> +#define AST_I2CD_INTR_SCL_TIMEOUT (0x1 << 6)<br>
> +#define AST_I2CD_INTR_ABNORMAL (0x1 << 5)<br>
> +#define AST_I2CD_INTR_NORMAL_STOP (0x1 << 4)<br>
> +#define AST_I2CD_INTR_ARBIT_LOSS (0x1 << 3)<br>
> +#define AST_I2CD_INTR_RX_DONE (0x1 << 2)<br>
> +#define AST_I2CD_INTR_TX_NAK (0x1 << 1)<br>
> +#define AST_I2CD_INTR_TX_ACK (0x1 << 0)<br>
> +<br>
> +/* 0x14 : I2CD Command/Status Register */<br>
> +#define AST_I2CD_SDA_OE (0x1 << 28)<br>
> +#define AST_I2CD_SDA_O (0x1 << 27)<br>
> +#define AST_I2CD_SCL_OE (0x1 << 26)<br>
> +#define AST_I2CD_SCL_O (0x1 << 25)<br>
> +#define AST_I2CD_TX_TIMING (0x1 << 24) // 0 ~3<br>
> +#define AST_I2CD_TX_STATUS (0x1 << 23)<br>
> +<br>
> +// Tx State Machine<br>
> +#define AST_I2CD_IDLE 0x0<br>
> +#define AST_I2CD_MACTIVE 0x8<br>
> +#define AST_I2CD_MSTART 0x9<br>
> +#define AST_I2CD_MSTARTR 0xa<br>
> +#define AST_I2CD_MSTOP 0xb<br>
> +#define AST_I2CD_MTXD 0xc<br>
> +#define AST_I2CD_MRXACK 0xd<br>
> +#define AST_I2CD_MRXD 0xe<br>
> +#define AST_I2CD_MTXACK 0xf<br>
> +#define AST_I2CD_SWAIT 0x1<br>
> +#define AST_I2CD_SRXD 0x4<br>
> +#define AST_I2CD_STXACK 0x5<br>
> +#define AST_I2CD_STXD 0x6<br>
> +#define AST_I2CD_SRXACK 0x7<br>
> +#define AST_I2CD_RECOVER 0x3<br>
> +<br>
> +#define AST_I2CD_SCL_LINE_STS (0x1 << 18)<br>
> +#define AST_I2CD_SDA_LINE_STS (0x1 << 17)<br>
> +#define AST_I2CD_BUS_BUSY_STS (0x1 << 16)<br>
> +#define AST_I2CD_SDA_OE_OUT_DIR (0x1 << 15)<br>
> +#define AST_I2CD_SDA_O_OUT_DIR (0x1 << 14)<br>
> +#define AST_I2CD_SCL_OE_OUT_DIR (0x1 << 13)<br>
> +#define AST_I2CD_SCL_O_OUT_DIR (0x1 << 12)<br>
> +#define AST_I2CD_BUS_RECOVER_CMD (0x1 << 11)<br>
> +#define AST_I2CD_S_ALT_EN (0x1 << 10)<br>
> +// 0 : DMA Buffer, 1: Pool Buffer<br>
> +//AST1070 DMA register<br>
> +#define AST_I2CD_RX_DMA_ENABLE (0x1 << 9)<br>
> +#define AST_I2CD_TX_DMA_ENABLE (0x1 << 8)<br>
> +<br>
> +/* Command Bit */<br>
> +#define AST_I2CD_RX_BUFF_ENABLE (0x1 << 7)<br>
> +#define AST_I2CD_TX_BUFF_ENABLE (0x1 << 6)<br>
> +#define AST_I2CD_M_STOP_CMD (0x1 << 5)<br>
> +#define AST_I2CD_M_S_RX_CMD_LAST (0x1 << 4)<br>
> +#define AST_I2CD_M_RX_CMD (0x1 << 3)<br>
> +#define AST_I2CD_S_TX_CMD (0x1 << 2)<br>
> +#define AST_I2CD_M_TX_CMD (0x1 << 1)<br>
> +#define AST_I2CD_M_START_CMD (0x1 )<br>
> +<br>
> +/* 0x18 : I2CD Slave Device Address Register */<br>
> +<br>
> +/* 0x1C : I2CD Pool Buffer Control Register */<br>
> +#define AST_I2CD_RX_BUF_ADDR_GET(x) (((x) >> 24) & 0xff)<br>
> +#define AST_I2CD_RX_BUF_END_ADDR_SET(<wbr>x) ((x) << 16)<br>
> +#define AST_I2CD_TX_DATA_BUF_END_SET(<wbr>x) (((x) & 0xff) << 8)<br>
> +#define AST_I2CD_RX_DATA_BUF_GET(x) (((x) >> 8) & 0xff)<br>
> +#define AST_I2CD_BUF_BASE_ADDR_SET(x) ((x) & 0x3f)<br>
> +<br>
> +/* 0x20 : I2CD Transmit/Receive Byte Buffer Register */<br>
> +#define AST_I2CD_GET_MODE(x) (((x) >> 8) & 0x1)<br>
> +<br>
> +#define AST_I2CD_RX_BYTE_BUFFER (0xff << 8)<br>
> +#define AST_I2CD_TX_BYTE_BUFFER (0xff )<br>
> +<br>
> +//1. usage flag , 2 size, 3. request address<br>
> +/* Use platform_data instead of module parameters */<br>
> +/* Fast Mode = 400 kHz, Standard = 100 kHz */<br>
> +//static int clock = 100; /* Default: 100 kHz */<br>
> +<br>
> +#define AST_I2CD_CMDS (AST_I2CD_BUS_RECOVER_CMD_EN | \<br>
> + AST_I2CD_M_STOP_CMD | \<br>
> + AST_I2CD_M_S_RX_CMD_LAST | \<br>
> + AST_I2CD_M_RX_CMD | \<br>
> + AST_I2CD_M_TX_CMD | \<br>
> + AST_I2CD_M_START_CMD)<br>
> +<br>
> +#endif /* _ASPEED_REGS_I2C_H_ */<br>
> --<br>
> 2.8.0.rc3.226.g39d4020<br>
><br>
</div></div>> ______________________________<wbr>_________________<br>
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</blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature" data-smartmail="gmail_signature"><div><b>M</b>axim <b>S</b>loyko</div></div>
</div></div>