<div dir="ltr">Ping!</div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Sep 19, 2016 at 10:26 AM, <span dir="ltr"><<a href="mailto:maxims@google.com" target="_blank">maxims@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Maxim Sloyko <<a href="mailto:maxims@google.com">maxims@google.com</a>><br>
<br>
The driver is limited: only single master mode is supported and only<br>
byte-by-byte reads and writes are supported, no DMA or Pool Buffers.<br>
<br>
Also, pin function configuration is performed by the I2C driver, because<br>
there is no pinctrl driver at the moment.<br>
---<br>
arch/arm/dts/Makefile | 2 +<br>
arch/arm/dts/aspeed-g5-evb.dts | 28 ++<br>
arch/arm/dts/aspeed-g5.dtsi | 392 ++++++++++++++++++++++++++++<br>
arch/arm/include/asm/arch-<wbr>aspeed/ast_scu.h | 6 +<br>
arch/arm/include/asm/arch-<wbr>aspeed/regs-scu.h | 74 +++---<br>
arch/arm/mach-aspeed/ast-scu.c | 31 ++-<br>
board/aspeed/ast-g5/ast-g5.c | 2 +-<br>
configs/ast_g5_defconfig | 4 +-<br>
drivers/i2c/Kconfig | 6 +<br>
drivers/i2c/Makefile | 1 +<br>
drivers/i2c/ast_i2c.c | 306 ++++++++++++++++++++++<br>
drivers/i2c/ast_i2c.h | 155 +++++++++++<br>
12 files changed, 970 insertions(+), 37 deletions(-)<br>
create mode 100644 arch/arm/dts/aspeed-g5-evb.dts<br>
create mode 100644 arch/arm/dts/aspeed-g5.dtsi<br>
create mode 100644 drivers/i2c/ast_i2c.c<br>
create mode 100644 drivers/i2c/ast_i2c.h<br>
<br>
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile<br>
index d1f8e22..f1f1ab3 100644<br>
--- a/arch/arm/dts/Makefile<br>
+++ b/arch/arm/dts/Makefile<br>
@@ -233,6 +233,8 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \<br>
k2e-evm.dtb \<br>
k2g-evm.dtb<br>
<br>
+dtb-y += aspeed-g5-evb.dtb<br>
+<br>
targets += $(dtb-y)<br>
<br>
# Add any required device tree compiler flags here<br>
diff --git a/arch/arm/dts/aspeed-g5-evb.<wbr>dts b/arch/arm/dts/aspeed-g5-evb.<wbr>dts<br>
new file mode 100644<br>
index 0000000..95dc77a<br>
--- /dev/null<br>
+++ b/arch/arm/dts/aspeed-g5-evb.<wbr>dts<br>
@@ -0,0 +1,28 @@<br>
+/dts-v1/;<br>
+<br>
+#include "aspeed-g5.dtsi"<br>
+<br>
+/ {<br>
+ memory {<br>
+ device_type = "memory";<br>
+ reg = <0x80000000 0x20000000>;<br>
+ };<br>
+<br>
+ aliases {<br>
+ i2c1 = &i2c0;<br>
+ i2c4 = &i2c3;<br>
+ i2c8 = &i2c7;<br>
+ };<br>
+};<br>
+<br>
+&i2c0 {<br>
+ status = "okay";<br>
+};<br>
+<br>
+&i2c3 {<br>
+ status = "okay";<br>
+};<br>
+<br>
+&i2c7 {<br>
+ status = "okay";<br>
+};<br>
diff --git a/arch/arm/dts/aspeed-g5.dtsi b/arch/arm/dts/aspeed-g5.dtsi<br>
new file mode 100644<br>
index 0000000..f1ff9e3<br>
--- /dev/null<br>
+++ b/arch/arm/dts/aspeed-g5.dtsi<br>
@@ -0,0 +1,392 @@<br>
+#include <dt-bindings/interrupt-<wbr>controller/arm-gic.h><br>
+<br>
+#include "skeleton.dtsi"<br>
+<br>
+/ {<br>
+ model = "Aspeed BMC";<br>
+ compatible = "aspeed,ast2500";<br>
+ #address-cells = <1>;<br>
+ #size-cells = <1>;<br>
+ interrupt-parent = <&vic>;<br>
+<br>
+ cpus {<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+<br>
+ cpu@0 {<br>
+ compatible = "arm,arm1176", "arm,armv6";<br>
+ device_type = "cpu";<br>
+ reg = <0>;<br>
+ };<br>
+ };<br>
+<br>
+ ahb {<br>
+ compatible = "simple-bus";<br>
+ #address-cells = <1>;<br>
+ #size-cells = <1>;<br>
+ ranges;<br>
+<br>
+ pinmux: pinmux@1e6e2000 {<br>
+ reg= <0x1e6e2000 0x1000>;<br>
+ compatible = "aspeed,ast2500-pinctrl";<br>
+ };<br>
+<br>
+ vic: interrupt-controller@1e6c0080 {<br>
+ compatible = "aspeed,ast2500-vic";<br>
+ interrupt-controller;<br>
+ #interrupt-cells = <1>;<br>
+ valid-sources = <0xfefff7ff 0x0807ffff>;<br>
+ reg = <0x1e6c0080 0x80>;<br>
+ };<br>
+<br>
+ mac0: ethernet@1e660000 {<br>
+ compatible = "faraday,ftgmac100";<br>
+ reg = <0x1e660000 0x180>;<br>
+ interrupts = <2>;<br>
+ aspeed-g5-interface;<br>
+ no-hw-checksum;<br>
+ status = "disabled";<br>
+ };<br>
+<br>
+ mac1: ethernet@1e680000 {<br>
+ compatible = "faraday,ftgmac100";<br>
+ reg = <0x1e680000 0x180>;<br>
+ interrupts = <3>;<br>
+ aspeed-g5-interface;<br>
+ no-hw-checksum;<br>
+ status = "disabled";<br>
+ };<br>
+<br>
+ apb {<br>
+ compatible = "simple-bus";<br>
+ #address-cells = <1>;<br>
+ #size-cells = <1>;<br>
+ ranges;<br>
+<br>
+ clk_clkin: clk_clkin@1e6e2070 {<br>
+ #clock-cells = <0>;<br>
+ compatible = "aspeed,g5-clkin-clock";<br>
+ reg = <0x1e6e2070 0x04>;<br>
+ };<br>
+<br>
+ clk_hpll: clk_hpll@1e6e2024 {<br>
+ #clock-cells = <0>;<br>
+ compatible = "aspeed,g5-hpll-clock";<br>
+ reg = <0x1e6e2024 0x4>;<br>
+ clocks = <&clk_clkin>;<br>
+ };<br>
+<br>
+ clk_ahb: clk_ahb@1e6e2070 {<br>
+ #clock-cells = <0>;<br>
+ compatible = "aspeed,g5-ahb-clock";<br>
+ reg = <0x1e6e2070 0x4>;<br>
+ clocks = <&clk_hpll>;<br>
+ };<br>
+<br>
+ clk_apb: clk_apb@1e6e2008 {<br>
+ #clock-cells = <0>;<br>
+ compatible = "aspeed,g5-apb-clock";<br>
+ reg = <0x1e6e2008 0x4>;<br>
+ clocks = <&clk_hpll>;<br>
+ };<br>
+<br>
+ clk_uart: clk_uart@1e6e2008 {<br>
+ #clock-cells = <0>;<br>
+ compatible = "aspeed,uart-clock";<br>
+ reg = <0x1e6e202c 0x4>;<br>
+ };<br>
+<br>
+ sram@1e720000 {<br>
+ compatible = "mmio-sram";<br>
+ reg = <0x1e720000 0x9000>; // 36K<br>
+ };<br>
+<br>
+ timer: timer@1e782000 {<br>
+ compatible = "aspeed,ast2500-timer";<br>
+ reg = <0x1e782000 0x90>;<br>
+ // The moxart_timer driver registers only one<br>
+ // interrupt and assumes it's for timer 1<br>
+ //interrupts = <16 17 18 35 36 37 38 39>;<br>
+ interrupts = <16>;<br>
+ clocks = <&clk_apb>;<br>
+ };<br>
+<br>
+ ibt: ibt@1e789140 {<br>
+ compatible = "aspeed,bt-host";<br>
+ reg = <0x1e789140 0x18>;<br>
+ interrupts = <8>;<br>
+ };<br>
+<br>
+ wdt1: wdt@1e785000 {<br>
+ compatible = "aspeed,ast2500-wdt";<br>
+ reg = <0x1e785000 0x1c>;<br>
+ };<br>
+<br>
+ wdt2: wdt@1e785020 {<br>
+ compatible = "aspeed,ast2500-wdt";<br>
+ reg = <0x1e785020 0x1c>;<br>
+ status = "disabled";<br>
+ };<br>
+<br>
+ wdt3: wdt@1e785040 {<br>
+ compatible = "aspeed,wdt";<br>
+ reg = <0x1e785074 0x1c>;<br>
+ status = "disabled";<br>
+ };<br>
+<br>
+ gpio: gpio@1e780000 {<br>
+ #gpio-cells = <2>;<br>
+ gpio-controller;<br>
+ compatible = "aspeed,ast2500-gpio";<br>
+ reg = <0x1e780000 0x1000>;<br>
+ interrupts = <20>;<br>
+ };<br>
+<br>
+ uart1: serial@1e783000 {<br>
+ compatible = "ns16550a";<br>
+ reg = <0x1e783000 0x1000>;<br>
+ reg-shift = <2>;<br>
+ interrupts = <9>;<br>
+ clocks = <&clk_uart>;<br>
+ no-loopback-test;<br>
+ status = "disabled";<br>
+ };<br>
+<br>
+ uart2: serial@1e78d000 {<br>
+ compatible = "ns16550a";<br>
+ reg = <0x1e78d000 0x1000>;<br>
+ reg-shift = <2>;<br>
+ interrupts = <32>;<br>
+ clocks = <&clk_uart>;<br>
+ no-loopback-test;<br>
+ status = "disabled";<br>
+ };<br>
+<br>
+ uart3: serial@1e78e000 {<br>
+ compatible = "ns16550a";<br>
+ reg = <0x1e78e000 0x1000>;<br>
+ reg-shift = <2>;<br>
+ interrupts = <33>;<br>
+ clocks = <&clk_uart>;<br>
+ no-loopback-test;<br>
+ status = "disabled";<br>
+ };<br>
+<br>
+ uart4: serial@1e78f000 {<br>
+ compatible = "ns16550a";<br>
+ reg = <0x1e78f000 0x1000>;<br>
+ reg-shift = <2>;<br>
+ interrupts = <34>;<br>
+ clocks = <&clk_uart>;<br>
+ no-loopback-test;<br>
+ status = "disabled";<br>
+ };<br>
+<br>
+ uart5: serial@1e784000 {<br>
+ compatible = "ns16550a";<br>
+ reg = <0x1e784000 0x1000>;<br>
+ reg-shift = <2>;<br>
+ interrupts = <10>;<br>
+ clocks = <&clk_uart>;<br>
+ current-speed = <38400>;<br>
+ no-loopback-test;<br>
+ status = "disabled";<br>
+ };<br>
+<br>
+ uart6: serial@1e787000 {<br>
+ compatible = "ns16550a";<br>
+ reg = <0x1e787000 0x1000>;<br>
+ reg-shift = <2>;<br>
+ interrupts = <10>;<br>
+ clocks = <&clk_uart>;<br>
+ no-loopback-test;<br>
+ status = "disabled";<br>
+ };<br>
+<br>
+ i2c: i2c@1e78a000 {<br>
+ #address-cells = <1>;<br>
+ #size-cells = <1>;<br>
+ #interrupt-cells = <1>;<br>
+<br>
+ compatible = "aspeed,ast2500-i2c-<wbr>controller";<br>
+ reg = <0x1e78a000 0x40>;<br>
+ ranges = <0 0x1e78a000 0x1000>;<br>
+ interrupts = <12>;<br>
+ clocks = <&clk_apb>;<br>
+ buffer = <0x1e78a200 0x10>;<br>
+ clock-ranges;<br>
+ interrupt-controller;<br>
+<br>
+ i2c0: i2c-bus@40 {<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+ reg = <0x40 0x40>;<br>
+ compatible = "aspeed,ast2500-i2c-bus";<br>
+ bus = <0>;<br>
+ clock-frequency = <100000>;<br>
+ status = "disabled";<br>
+ interrupts = <0>;<br>
+ interrupt-parent = <&i2c>;<br>
+ buffer;<br>
+ };<br>
+<br>
+ i2c1: i2c-bus@80 {<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+ reg = <0x80 0x40>;<br>
+ compatible = "aspeed,ast2500-i2c-bus";<br>
+ bus = <1>;<br>
+ clock-frequency = <100000>;<br>
+ status = "disabled";<br>
+ interrupts = <1>;<br>
+ buffer = <0x10 0x10>;<br>
+ };<br>
+<br>
+ i2c2: i2c-bus@c0 {<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+ reg = <0xC0 0x40>;<br>
+ compatible = "aspeed,ast2500-i2c-bus";<br>
+ bus = <2>;<br>
+ clock-frequency = <100000>;<br>
+ status = "disabled";<br>
+ interrupts = <2>;<br>
+ buffer = <0x20 0x10>;<br>
+ };<br>
+<br>
+ i2c3: i2c-bus@100 {<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+ reg = <0x100 0x40>;<br>
+ compatible = "aspeed,ast2500-i2c-bus";<br>
+ bus = <3>;<br>
+ clock-frequency = <100000>;<br>
+ status = "disabled";<br>
+ interrupts = <3>;<br>
+ buffer = <0x30 0x10>;<br>
+ };<br>
+<br>
+ i2c4: i2c-bus@140 {<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+ reg = <0x140 0x40>;<br>
+ compatible = "aspeed,ast2500-i2c-bus";<br>
+ bus = <4>;<br>
+ clock-frequency = <100000>;<br>
+ status = "disabled";<br>
+ interrupts = <4>;<br>
+ buffer = <0x40 0x10>;<br>
+ };<br>
+<br>
+ i2c5: i2c-bus@180 {<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+ reg = <0x180 0x40>;<br>
+ compatible = "aspeed,ast2500-i2c-bus";<br>
+ bus = <5>;<br>
+ clock-frequency = <100000>;<br>
+ status = "disabled";<br>
+ interrupts = <5>;<br>
+ buffer = <0x50 0x10>;<br>
+ };<br>
+<br>
+ i2c6: i2c-bus@1c0 {<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+ reg = <0x1C0 0x40>;<br>
+ compatible = "aspeed,ast2500-i2c-bus";<br>
+ bus = <6>;<br>
+ clock-frequency = <100000>;<br>
+ status = "disabled";<br>
+ interrupts = <6>;<br>
+ buffer = <0x60 0x10>;<br>
+ };<br>
+<br>
+ i2c7: i2c-bus@300 {<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+ reg = <0x300 0x40>;<br>
+ compatible = "aspeed,ast2500-i2c-bus";<br>
+ bus = <7>;<br>
+ clock-frequency = <100000>;<br>
+ status = "disabled";<br>
+ interrupts = <7>;<br>
+ buffer = <0x70 0x10>;<br>
+ };<br>
+<br>
+ i2c8: i2c-bus@340 {<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+ reg = <0x340 0x40>;<br>
+ compatible = "aspeed,ast2500-i2c-bus";<br>
+ bus = <8>;<br>
+ clock-frequency = <100000>;<br>
+ status = "disabled";<br>
+ interrupts = <8>;<br>
+ buffer = <0x80 0x10>;<br>
+ };<br>
+<br>
+ i2c9: i2c-bus@380 {<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+ reg = <0x380 0x40>;<br>
+ compatible = "aspeed,ast2500-i2c-bus";<br>
+ bus = <9>;<br>
+ clock-frequency = <100000>;<br>
+ status = "disabled";<br>
+ interrupts = <9>;<br>
+ buffer = <0x90 0x10>;<br>
+ };<br>
+<br>
+ i2c10: i2c-bus@3c0 {<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+ reg = <0x3c0 0x40>;<br>
+ compatible = "aspeed,ast2500-i2c-bus";<br>
+ bus = <10>;<br>
+ clock-frequency = <100000>;<br>
+ status = "disabled";<br>
+ interrupts = <10>;<br>
+ buffer = <0xa0 0x10>;<br>
+ };<br>
+<br>
+ i2c11: i2c-bus@400 {<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+ reg = <0x400 0x40>;<br>
+ compatible = "aspeed,ast2500-i2c-bus";<br>
+ bus = <11>;<br>
+ clock-frequency = <100000>;<br>
+ status = "disabled";<br>
+ interrupts = <11>;<br>
+ buffer = <0xb0 0x10>;<br>
+ };<br>
+<br>
+ i2c12: i2c-bus@440 {<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+ reg = <0x440 0x40>;<br>
+ compatible = "aspeed,ast2500-i2c-bus";<br>
+ bus = <12>;<br>
+ clock-frequency = <100000>;<br>
+ status = "disabled";<br>
+ interrupts = <12>;<br>
+ buffer = <0xc0 0x10>;<br>
+ };<br>
+<br>
+ i2c13: i2c-bus@480 {<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+ reg = <0x480 0x40>;<br>
+ compatible = "aspeed,ast2500-i2c-bus";<br>
+ bus = <13>;<br>
+ clock-frequency = <100000>;<br>
+ status = "disabled";<br>
+ interrupts = <13>;<br>
+ buffer = <0xd0 0x10>;<br>
+ };<br>
+<br>
+ };<br>
+ };<br>
+ };<br>
+};<br>
diff --git a/arch/arm/include/asm/arch-<wbr>aspeed/ast_scu.h b/arch/arm/include/asm/arch-<wbr>aspeed/ast_scu.h<br>
index d248416..80ebd6f 100644<br>
--- a/arch/arm/include/asm/arch-<wbr>aspeed/ast_scu.h<br>
+++ b/arch/arm/include/asm/arch-<wbr>aspeed/ast_scu.h<br>
@@ -38,6 +38,7 @@ extern void ast_scu_get_who_init_dram(<wbr>void);<br>
extern u32 ast_get_clk_source(void);<br>
extern u32 ast_get_h_pll_clk(void);<br>
extern u32 ast_get_ahbclk(void);<br>
+extern u32 ast_get_apbclk(void);<br>
<br>
extern u32 ast_scu_get_vga_memsize(void);<br>
<br>
@@ -45,4 +46,9 @@ extern void ast_scu_init_eth(u8 num);<br>
extern void ast_scu_multi_func_eth(u8 num);<br>
extern void ast_scu_multi_func_romcs(u8 num);<br>
<br>
+/* Enable I2C controller and pins for a particular device.<br>
+ * Device numbering starts at 1<br>
+ */<br>
+extern void ast_scu_enable_i2c(u8 num);<br>
+<br>
#endif<br>
diff --git a/arch/arm/include/asm/arch-<wbr>aspeed/regs-scu.h b/arch/arm/include/asm/arch-<wbr>aspeed/regs-scu.h<br>
index b89df82..92ce84a 100644<br>
--- a/arch/arm/include/asm/arch-<wbr>aspeed/regs-scu.h<br>
+++ b/arch/arm/include/asm/arch-<wbr>aspeed/regs-scu.h<br>
@@ -10,8 +10,8 @@<br>
* 1. 2012/12/29 Ryan Chen Create<br>
*<br>
******************************<wbr>******************************<wbr>********************/<br>
-#ifndef __AST_SCU_H<br>
-#define __AST_SCU_H 1<br>
+#ifndef __AST_REGS_SCU_H<br>
+#define __AST_REGS_SCU_H 1<br>
<br>
#include <asm/arch/aspeed.h><br>
<br>
@@ -830,49 +830,50 @@<br>
/* AST_SCU_FUN_PIN_CTRL5 0x90 - Multi-function Pin Control#5 */<br>
#define SCU_FUN_PIN_SPICS1 (0x1 << 31)<br>
#define SCU_FUN_PIN_LPC_PLUS (0x1 << 30)<br>
-#define SCU_FUC_PIN_USB20_HOST (0x1 << 29)<br>
-#define SCU_FUC_PIN_USB11_PORT4 (0x1 << 28)<br>
-#define SCU_FUC_PIN_I2C14 (0x1 << 27)<br>
-#define SCU_FUC_PIN_I2C13 (0x1 << 26)<br>
-#define SCU_FUC_PIN_I2C12 (0x1 << 25)<br>
-#define SCU_FUC_PIN_I2C11 (0x1 << 24)<br>
-#define SCU_FUC_PIN_I2C10 (0x1 << 23)<br>
-#define SCU_FUC_PIN_I2C9 (0x1 << 22)<br>
-#define SCU_FUC_PIN_I2C8 (0x1 << 21)<br>
-#define SCU_FUC_PIN_I2C7 (0x1 << 20)<br>
-#define SCU_FUC_PIN_I2C6 (0x1 << 19)<br>
-#define SCU_FUC_PIN_I2C5 (0x1 << 18)<br>
-#define SCU_FUC_PIN_I2C4 (0x1 << 17)<br>
-#define SCU_FUC_PIN_I2C3 (0x1 << 16)<br>
-#define SCU_FUC_PIN_MII2_RX_DWN_DIS (0x1 << 15)<br>
-#define SCU_FUC_PIN_MII2_TX_DWN_DIS (0x1 << 14)<br>
-#define SCU_FUC_PIN_MII1_RX_DWN_DIS (0x1 << 13)<br>
-#define SCU_FUC_PIN_MII1_TX_DWN_DIS (0x1 << 12)<br>
-<br>
-#define SCU_FUC_PIN_MII2_TX_DRIV(x) (x << 10)<br>
-#define SCU_FUC_PIN_MII2_TX_DRIV_MASK (0x3 << 10)<br>
-#define SCU_FUC_PIN_MII1_TX_DRIV(x) (x << 8)<br>
-#define SCU_FUC_PIN_MII1_TX_DRIV_MASK (0x3 << 8)<br>
+#define SCU_FUN_PIN_USB20_HOST (0x1 << 29)<br>
+#define SCU_FUN_PIN_USB11_PORT4 (0x1 << 28)<br>
+#define SCU_FUN_PIN_I2C14 (0x1 << 27)<br>
+#define SCU_FUN_PIN_I2C13 (0x1 << 26)<br>
+#define SCU_FUN_PIN_I2C12 (0x1 << 25)<br>
+#define SCU_FUN_PIN_I2C11 (0x1 << 24)<br>
+#define SCU_FUN_PIN_I2C10 (0x1 << 23)<br>
+#define SCU_FUN_PIN_I2C9 (0x1 << 22)<br>
+#define SCU_FUN_PIN_I2C8 (0x1 << 21)<br>
+#define SCU_FUN_PIN_I2C7 (0x1 << 20)<br>
+#define SCU_FUN_PIN_I2C6 (0x1 << 19)<br>
+#define SCU_FUN_PIN_I2C5 (0x1 << 18)<br>
+#define SCU_FUN_PIN_I2C4 (0x1 << 17)<br>
+#define SCU_FUN_PIN_I2C3 (0x1 << 16)<br>
+#define SCU_FUN_PIN_I2C(n) (0x1 << (16 + (n) - 3))<br>
+#define SCU_FUN_PIN_MII2_RX_DWN_DIS (0x1 << 15)<br>
+#define SCU_FUN_PIN_MII2_TX_DWN_DIS (0x1 << 14)<br>
+#define SCU_FUN_PIN_MII1_RX_DWN_DIS (0x1 << 13)<br>
+#define SCU_FUN_PIN_MII1_TX_DWN_DIS (0x1 << 12)<br>
+<br>
+#define SCU_FUN_PIN_MII2_TX_DRIV(x) (x << 10)<br>
+#define SCU_FUN_PIN_MII2_TX_DRIV_MASK (0x3 << 10)<br>
+#define SCU_FUN_PIN_MII1_TX_DRIV(x) (x << 8)<br>
+#define SCU_FUN_PIN_MII1_TX_DRIV_MASK (0x3 << 8)<br>
<br>
#define MII_NORMAL_DRIV 0x0<br>
#define MII_HIGH_DRIV 0x2<br>
<br>
-#define SCU_FUC_PIN_UART6 (0x1 << 7)<br>
-#define SCU_FUC_PIN_ROM_16BIT (0x1 << 6)<br>
-#define SCU_FUC_PIN_DIGI_V_OUT(x) (x)<br>
-#define SCU_FUC_PIN_DIGI_V_OUT_MASK (0x3)<br>
+#define SCU_FUN_PIN_UART6 (0x1 << 7)<br>
+#define SCU_FUN_PIN_ROM_16BIT (0x1 << 6)<br>
+#define SCU_FUN_PIN_DIGI_V_OUT(x) (x)<br>
+#define SCU_FUN_PIN_DIGI_V_OUT_MASK (0x3)<br>
<br>
#define VIDEO_DISABLE 0x0<br>
#define VIDEO_12BITS 0x1<br>
#define VIDEO_24BITS 0x2<br>
//#define VIDEO_DISABLE 0x3<br>
<br>
-#define SCU_FUC_PIN_USB11_PORT2 (0x1 << 3)<br>
-#define SCU_FUC_PIN_SD1_8BIT (0x1 << 3)<br>
+#define SCU_FUN_PIN_USB11_PORT2 (0x1 << 3)<br>
+#define SCU_FUN_PIN_SD1_8BIT (0x1 << 3)<br>
<br>
-#define SCU_FUC_PIN_MAC1_MDIO (0x1 << 2)<br>
-#define SCU_FUC_PIN_SD2 (0x1 << 1)<br>
-#define SCU_FUC_PIN_SD1 (0x1 << 0)<br>
+#define SCU_FUN_PIN_MAC1_MDIO (0x1 << 2)<br>
+#define SCU_FUN_PIN_SD2 (0x1 << 1)<br>
+#define SCU_FUN_PIN_SD1 (0x1 << 0)<br>
<br>
<br>
/* AST_SCU_FUN_PIN_CTRL6 0x94 - Multi-function Pin Control#6*/<br>
@@ -914,6 +915,11 @@<br>
#define SCU_FUN_PIN_ROMA4 (0x1 << 18)<br>
#define SCU_FUN_PIN_ROMA3 (0x1 << 17)<br>
#define SCU_FUN_PIN_ROMA2 (0x1 << 16)<br>
+/* AST2500 only */<br>
+#define SCU_FUN_PIN_SDA2 (0x1 << 15)<br>
+#define SCU_FUN_PIN_SCL2 (0x1 << 14)<br>
+#define SCU_FUN_PIN_SDA1 (0x1 << 13)<br>
+#define SCU_FUN_PIN_SCL1 (0x1 << 12)<br>
<br>
/* AST_SCU_FUN_PIN_CTRL9 0xA8 - Multi-function Pin Control#9 */<br>
#define SCU_FUN_PIN_ROMA21 (0x1 << 3)<br>
diff --git a/arch/arm/mach-aspeed/ast-<wbr>scu.c b/arch/arm/mach-aspeed/ast-<wbr>scu.c<br>
index 0cc0d67..31cea60 100644<br>
--- a/arch/arm/mach-aspeed/ast-<wbr>scu.c<br>
+++ b/arch/arm/mach-aspeed/ast-<wbr>scu.c<br>
@@ -250,6 +250,7 @@ u32 ast_get_ahbclk(void)<br>
return ((hpll / axi_div) / ahb_div);<br>
}<br>
<br>
+<br>
#else /* ! AST_SOC_G5 */<br>
<br>
u32 ast_get_h_pll_clk(void)<br>
@@ -318,6 +319,14 @@ u32 ast_get_ahbclk(void)<br>
<br>
#endif /* AST_SOC_G5 */<br>
<br>
+u32 ast_get_apbclk(void)<br>
+{<br>
+ u32 h_pll = ast_get_h_pll_clk();<br>
+ u32 apb_div = SCU_GET_PCLK_DIV(ast_scu_read(<wbr>AST_SCU_CLK_SEL));<br>
+ return h_pll / apb_div;<br>
+}<br>
+<br>
+<br>
void ast_scu_show_system_info(void)<br>
{<br>
<br>
@@ -394,7 +403,7 @@ void ast_scu_multi_func_eth(u8 num)<br>
AST_SCU_FUN_PIN_CTRL1);<br>
<br>
ast_scu_write(ast_scu_read(<wbr>AST_SCU_FUN_PIN_CTRL5) |<br>
- SCU_FUC_PIN_MAC1_MDIO,<br>
+ SCU_FUN_PIN_MAC1_MDIO,<br>
AST_SCU_FUN_PIN_CTRL5);<br>
<br>
break;<br>
@@ -496,3 +505,23 @@ void ast_scu_get_who_init_dram(<wbr>void)<br>
break;<br>
}<br>
}<br>
+<br>
+void ast_scu_enable_i2c(u8 num)<br>
+{<br>
+ /* Enable I2C Controllers */<br>
+ clrbits_le32(AST_SCU_BASE + AST_SCU_RESET, SCU_RESET_I2C);<br>
+<br>
+ if (num < 3) {<br>
+#ifdef AST_SOC_G5<br>
+ if (num == 1) {<br>
+ setbits_le32(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL8,<br>
+ SCU_FUN_PIN_SDA1 | SCU_FUN_PIN_SCL1);<br>
+ } else {<br>
+ setbits_le32(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL8,<br>
+ SCU_FUN_PIN_SDA2 | SCU_FUN_PIN_SCL2);<br>
+ }<br>
+#endif<br>
+ } else {<br>
+ setbits_le32(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL5, SCU_FUN_PIN_I2C(num));<br>
+ }<br>
+}<br>
diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c<br>
index 81ea88a..03ce0de 100644<br>
--- a/board/aspeed/ast-g5/ast-g5.c<br>
+++ b/board/aspeed/ast-g5/ast-g5.c<br>
@@ -36,6 +36,7 @@<br>
#include <common.h><br>
#include <netdev.h><br>
#include <asm/arch/ast_scu.h><br>
+#include <asm/arch/regs-scu.h><br>
#include <asm/arch/ast-sdmc.h><br>
#include <asm/io.h><br>
<br>
@@ -52,7 +53,6 @@ int board_init(void)<br>
{<br>
/* adress of boot parameters */<br>
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;<br>
- gd->flags = 0;<br>
return 0;<br>
}<br>
<br>
diff --git a/configs/ast_g5_defconfig b/configs/ast_g5_defconfig<br>
index b5f2b24..20b02a3 100644<br>
--- a/configs/ast_g5_defconfig<br>
+++ b/configs/ast_g5_defconfig<br>
@@ -1,4 +1,5 @@<br>
CONFIG_ARM=y<br>
+CONFIG_DEFAULT_DEVICE_TREE="<wbr>aspeed-g5"<br>
CONFIG_TARGET_AST_G5=y<br>
CONFIG_SPI_FLASH=y<br>
CONFIG_SYS_NS16550=y<br>
@@ -6,4 +7,5 @@ CONFIG_SYS_PROMPT="ast# "<br>
CONFIG_CMD_SAVEENV=y<br>
CONFIG_CMD_FLASH=y<br>
CONFIG_CMD_PING=y<br>
-CONFIG_CMD_DHCP=y<br>
\ No newline at end of file<br>
+CONFIG_CMD_DHCP=y<br>
+CONFIG_SYS_I2C_ASPEED=y<br>
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig<br>
index 9324c6c..6501e91 100644<br>
--- a/drivers/i2c/Kconfig<br>
+++ b/drivers/i2c/Kconfig<br>
@@ -65,6 +65,12 @@ config SYS_I2C_CADENCE<br>
Say yes here to select Cadence I2C Host Controller. This controller is<br>
e.g. used by Xilinx Zynq.<br>
<br>
+config SYS_I2C_AST<br>
+ tristate "Aspeed I2C Controller"<br>
+ depends on DM_I2C<br>
+ help<br>
+ Say yes here to select Aspeed I2C Host Controller.<br>
+<br>
config SYS_I2C_INTEL<br>
bool "Intel I2C/SMBUS driver"<br>
depends on DM_I2C<br>
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile<br>
index 167424d..89e046e 100644<br>
--- a/drivers/i2c/Makefile<br>
+++ b/drivers/i2c/Makefile<br>
@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o<br>
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o<br>
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o<br>
obj-$(CONFIG_SYS_I2C) += i2c_core.o<br>
+obj-$(CONFIG_SYS_I2C_AST) += ast_i2c.o<br>
obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o<br>
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o<br>
obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o<br>
diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c<br>
new file mode 100644<br>
index 0000000..144bf02<br>
--- /dev/null<br>
+++ b/drivers/i2c/ast_i2c.c<br>
@@ -0,0 +1,306 @@<br>
+/*<br>
+ * Copyright (C) 2016 Google, Inc<br>
+ *<br>
+ * SPDX-License-Identifier: GPL-2.0+<br>
+ */<br>
+<br>
+#include <common.h><br>
+#include <dm.h><br>
+#include <fdtdec.h><br>
+#include <i2c.h><br>
+<br>
+#include <asm/arch/ast_scu.h><br>
+#include <asm/arch/regs-scu.h><br>
+#include <asm/io.h><br>
+<br>
+#include "ast_i2c.h"<br>
+<br>
+#define I2C_TIMEOUT_US (100000)<br>
+#define I2C_SLEEP_STEP (20)<br>
+#define EI2C_TIMEOUT (1001)<br>
+<br>
+DECLARE_GLOBAL_DATA_PTR;<br>
+<br>
+struct ast_i2c {<br>
+ u32 id;<br>
+ struct ast_i2c_regs *regs;<br>
+ int speed;<br>
+};<br>
+<br>
+#define RETURN_IF_ERROR(expr) do {\<br>
+ int err = (expr);\<br>
+ if (err < 0) {\<br>
+ return err;\<br>
+ }\<br>
+} while (0)<br>
+<br>
+static u32 __get_clk_reg_val(u32 divider_ratio)<br>
+{<br>
+ unsigned int inc = 0, div;<br>
+ u32 scl_low, scl_high, data;<br>
+<br>
+ for (div = 0; divider_ratio >= 16; div++) {<br>
+ inc |= (divider_ratio & 1);<br>
+ divider_ratio >>= 1;<br>
+ }<br>
+ divider_ratio += inc;<br>
+ scl_low = (divider_ratio >> 1) - 1;<br>
+ scl_high = divider_ratio - scl_low - 2;<br>
+ data = 0x77700300 | (scl_high << 16) | (scl_low << 12) | div;<br>
+ return data;<br>
+}<br>
+<br>
+static inline void __ast_i2c_clear_interrupts(<wbr>struct ast_i2c_regs *i2c_base)<br>
+{<br>
+ writel(~0, &i2c_base->isr);<br>
+}<br>
+<br>
+static int __ast_i2c_init_bus(struct ast_i2c *i2c_bus)<br>
+{<br>
+ /* Reset device */<br>
+ writel(0, &i2c_bus->regs->fcr);<br>
+ /* Enable Master Mode. Assuming single-master. */<br>
+ debug("Enable Master for %p\n", i2c_bus->regs);<br>
+ setbits_le32(&i2c_bus->regs-><wbr>fcr,<br>
+ AST_I2CD_MASTER_EN<br>
+ | AST_I2CD_M_SDA_LOCK_EN<br>
+ | AST_I2CD_MULTI_MASTER_DIS | AST_I2CD_M_SCL_DRIVE_EN);<br>
+ debug("FCR: %p\n", &i2c_bus->regs->fcr);<br>
+ /* Enable Interrupts */<br>
+ writel(AST_I2CD_INTR_TX_ACK<br>
+ | AST_I2CD_INTR_TX_NAK<br>
+ | AST_I2CD_INTR_RX_DONE<br>
+ | AST_I2CD_INTR_BUS_RECOVER_DONE<br>
+ | AST_I2CD_INTR_NORMAL_STOP<br>
+ | AST_I2CD_INTR_ABNORMAL, &i2c_bus->regs->icr);<br>
+ return 0;<br>
+}<br>
+<br>
+static int ast_i2c_probe(struct udevice *dev)<br>
+{<br>
+ struct ast_i2c *i2c_bus = dev_get_priv(dev);<br>
+<br>
+ debug("Enabling I2C%u \n", dev->seq);<br>
+ ast_scu_enable_i2c(dev->seq);<br>
+<br>
+ i2c_bus->id = dev->seq;<br>
+ struct ast_i2c_regs *i2c_base =<br>
+ (struct ast_i2c_regs *)dev_get_addr(dev);<br>
+ i2c_bus->regs = i2c_base;<br>
+<br>
+ return __ast_i2c_init_bus(i2c_bus);<br>
+}<br>
+<br>
+static inline int __ast_i2c_wait_isr(struct ast_i2c_regs *i2c_base, u32 flag)<br>
+{<br>
+ int timeout = I2C_TIMEOUT_US;<br>
+ while (!(readl(&i2c_base->isr) & flag) && timeout > 0) {<br>
+ udelay(I2C_SLEEP_STEP);<br>
+ timeout -= I2C_SLEEP_STEP;<br>
+ }<br>
+<br>
+ __ast_i2c_clear_interrupts(<wbr>i2c_base);<br>
+ if (timeout <= 0)<br>
+ return -EI2C_TIMEOUT;<br>
+ return 0;<br>
+}<br>
+<br>
+static inline int __ast_i2c_send_stop(struct ast_i2c_regs *i2c_base)<br>
+{<br>
+ writel(AST_I2CD_M_STOP_CMD, &i2c_base->csr);<br>
+ RETURN_IF_ERROR(__ast_i2c_<wbr>wait_isr<br>
+ (i2c_base, AST_I2CD_INTR_NORMAL_STOP));<br>
+ return 0;<br>
+}<br>
+<br>
+static inline int __ast_i2c_wait_tx(struct ast_i2c_regs *i2c_base)<br>
+{<br>
+ int timeout = I2C_TIMEOUT_US;<br>
+ u32 flag = AST_I2CD_INTR_TX_ACK | AST_I2CD_INTR_TX_NAK;<br>
+ u32 status = readl(&i2c_base->isr) & flag;<br>
+ while (!status && timeout > 0) {<br>
+ status = readl(&i2c_base->isr) & flag;<br>
+ udelay(I2C_SLEEP_STEP);<br>
+ timeout -= I2C_SLEEP_STEP;<br>
+ }<br>
+<br>
+ int ret = 0;<br>
+ if (status == AST_I2CD_INTR_TX_NAK) {<br>
+ ret = -EREMOTEIO;<br>
+ }<br>
+<br>
+ if (timeout <= 0) {<br>
+ ret = -EI2C_TIMEOUT;<br>
+ }<br>
+<br>
+ __ast_i2c_clear_interrupts(<wbr>i2c_base);<br>
+ return ret;<br>
+}<br>
+<br>
+static inline int __ast_i2c_start_txn(struct ast_i2c_regs *i2c_base, u8 devaddr)<br>
+{<br>
+ /* Start and Send Device Address */<br>
+ writel(devaddr, &i2c_base->trbbr);<br>
+ writel(AST_I2CD_M_START_CMD | AST_I2CD_M_TX_CMD, &i2c_base->csr);<br>
+ RETURN_IF_ERROR(__ast_i2c_<wbr>wait_tx(i2c_base));<br>
+ return 0;<br>
+}<br>
+<br>
+static int __ast_i2c_read_data(struct ast_i2c *i2c_bus, u8 chip, u8 *buffer,<br>
+ int len)<br>
+{<br>
+ int i2c_error = 0;<br>
+ struct ast_i2c_regs *i2c_base = i2c_bus->regs;<br>
+<br>
+ i2c_error = __ast_i2c_start_txn(i2c_base, (chip << 1) | I2C_M_RD);<br>
+<br>
+ if (!i2c_error) {<br>
+ u32 i2c_cmd = AST_I2CD_M_RX_CMD;<br>
+ for (; len > 0; len--, buffer++) {<br>
+ if (len == 1) {<br>
+ i2c_cmd |= AST_I2CD_M_S_RX_CMD_LAST;<br>
+ }<br>
+ writel(i2c_cmd, &i2c_base->csr);<br>
+ RETURN_IF_ERROR(__ast_i2c_<wbr>wait_isr<br>
+ (i2c_base, AST_I2CD_INTR_RX_DONE));<br>
+ *buffer = AST_I2CD_RX_DATA_BUF_GET(<wbr>readl(&i2c_base->trbbr));<br>
+ }<br>
+ __ast_i2c_clear_interrupts(<wbr>i2c_base);<br>
+ }<br>
+ RETURN_IF_ERROR(__ast_i2c_<wbr>send_stop(i2c_base));<br>
+<br>
+ return i2c_error;<br>
+}<br>
+<br>
+static int __ast_i2c_write_data(struct ast_i2c *i2c_bus, u8 chip, u8 *buffer,<br>
+ int len)<br>
+{<br>
+ int i2c_error = 0;<br>
+ struct ast_i2c_regs *i2c_base = i2c_bus->regs;<br>
+<br>
+ i2c_error = __ast_i2c_start_txn(i2c_base, (chip << 1));<br>
+ for (; len > 0 && 0 == i2c_error; len--, buffer++) {<br>
+ writel(*buffer, &i2c_base->trbbr);<br>
+ writel(AST_I2CD_M_TX_CMD, &i2c_base->csr);<br>
+ i2c_error = __ast_i2c_wait_tx(i2c_base);<br>
+ }<br>
+ RETURN_IF_ERROR(__ast_i2c_<wbr>send_stop(i2c_base));<br>
+ return i2c_error;<br>
+}<br>
+<br>
+static int ast_i2c_deblock(struct udevice *dev)<br>
+{<br>
+ struct ast_i2c *i2c_bus = dev_get_priv(dev);<br>
+ struct ast_i2c_regs *i2c_base = i2c_bus->regs;<br>
+<br>
+ u32 csr = readl(&i2c_base->csr);<br>
+ debug("Bus hung (%x), attempting recovery\n", csr);<br>
+<br>
+ bool sda_high = csr & AST_I2CD_SDA_LINE_STS;<br>
+ bool scl_high = csr & AST_I2CD_SCL_LINE_STS;<br>
+ if (sda_high && scl_high) {<br>
+ /* Bus is idle, no deblocking needed. */<br>
+ return 0;<br>
+ } else if (sda_high) {<br>
+ /* Send stop command */<br>
+ RETURN_IF_ERROR(__ast_i2c_<wbr>send_stop(i2c_base));<br>
+ } else if (scl_high) {<br>
+ /* Possibly stuck slave */<br>
+ writel(AST_I2CD_BUS_RECOVER_<wbr>CMD, &i2c_base->csr);<br>
+ RETURN_IF_ERROR(__ast_i2c_<wbr>wait_isr<br>
+ (i2c_base, AST_I2CD_INTR_BUS_RECOVER_<wbr>DONE));<br>
+ } else {<br>
+ /* Just try to reinit the device. */<br>
+ RETURN_IF_ERROR(__ast_i2c_<wbr>init_bus(i2c_bus));<br>
+ }<br>
+<br>
+ return 0;<br>
+}<br>
+<br>
+static int ast_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)<br>
+{<br>
+ struct ast_i2c *i2c_bus = dev_get_priv(dev);<br>
+ int ret;<br>
+<br>
+ debug("i2c_xfer: %d messages\n", nmsgs);<br>
+ for (; nmsgs > 0; nmsgs--, msg++) {<br>
+ /* TODO: use this for repeated start */<br>
+ bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);<br>
+<br>
+ if (msg->flags & I2C_M_RD) {<br>
+ debug("i2c_read: chip=0x%x, len=0x%x, flags=0x%x\n",<br>
+ msg->addr, msg->len, msg->flags);<br>
+ ret =<br>
+ __ast_i2c_read_data(i2c_bus, msg->addr, msg->buf,<br>
+ msg->len);<br>
+ } else {<br>
+ debug("i2c_write: chip=0x%x, len=0x%x, flags=0x%x\n",<br>
+ msg->addr, msg->len, msg->flags);<br>
+ ret =<br>
+ __ast_i2c_write_data(i2c_bus, msg->addr, msg->buf,<br>
+ msg->len);<br>
+ }<br>
+ if (ret) {<br>
+ debug("%s: error (%d)\n", __func__, ret);<br>
+ return -EREMOTEIO;<br>
+ }<br>
+ }<br>
+<br>
+ return 0;<br>
+}<br>
+<br>
+static int ast_i2c_set_speed(struct udevice *dev, unsigned int speed)<br>
+{<br>
+ debug("Setting speed ofr I2C%d to <%u>\n", dev->seq, speed);<br>
+ if (!speed) {<br>
+ debug("No valid speed specified.\n");<br>
+ return -EINVAL;<br>
+ }<br>
+ struct ast_i2c *i2c_bus = dev_get_priv(dev);<br>
+<br>
+ i2c_bus->speed = speed;<br>
+ /* TODO: get this from device tree */<br>
+ u32 pclk = ast_get_apbclk();<br>
+ u32 divider = pclk / speed;<br>
+<br>
+ struct ast_i2c_regs *i2c_base = i2c_bus->regs;<br>
+ if (speed > 400000) {<br>
+ debug("Enabling High Speed\n");<br>
+ setbits_le32(&i2c_base->fcr, AST_I2CD_M_HIGH_SPEED_EN<br>
+ | AST_I2CD_M_SDA_DRIVE_1T_EN<br>
+ | AST_I2CD_SDA_DRIVE_1T_EN);<br>
+ writel(0x3, &i2c_base->cactcr2);<br>
+ writel(__get_clk_reg_val(<wbr>divider), &i2c_base->cactcr1);<br>
+ } else {<br>
+ debug("Enabling Normal Speed\n");<br>
+ writel(__get_clk_reg_val(<wbr>divider), &i2c_base->cactcr1);<br>
+ writel(AST_NO_TIMEOUT_CTRL, &i2c_base->cactcr2);<br>
+ }<br>
+<br>
+ __ast_i2c_clear_interrupts(<wbr>i2c_base);<br>
+ return 0;<br>
+}<br>
+<br>
+static const struct dm_i2c_ops ast_i2c_ops = {<br>
+ .xfer = ast_i2c_xfer,<br>
+ .set_bus_speed = ast_i2c_set_speed,<br>
+ .deblock = ast_i2c_deblock,<br>
+};<br>
+<br>
+static const struct udevice_id ast_i2c_ids[] = {<br>
+ {.compatible = "aspeed,ast2500-i2c-<wbr>controller",},<br>
+ {.compatible = "aspeed,ast2500-i2c-bus",},<br>
+ {},<br>
+};<br>
+<br>
+/* Tell GNU Indent to keep this as is: */<br>
+/* *INDENT-OFF* */<br>
+U_BOOT_DRIVER(i2c_aspeed) = {<br>
+ .name = "i2c_aspeed",<br>
+ .id = UCLASS_I2C,<br>
+ .of_match = ast_i2c_ids,<br>
+ .probe = ast_i2c_probe,<br>
+ .priv_auto_alloc_size = sizeof(struct ast_i2c),<br>
+ .ops = &ast_i2c_ops,<br>
+};<br>
+/* *INDENT-ON* */<br>
diff --git a/drivers/i2c/ast_i2c.h b/drivers/i2c/ast_i2c.h<br>
new file mode 100644<br>
index 0000000..e221b41<br>
--- /dev/null<br>
+++ b/drivers/i2c/ast_i2c.h<br>
@@ -0,0 +1,155 @@<br>
+/*<br>
+ * Copyright (C) 2016 Google, Inc<br>
+ *<br>
+ * SPDX-License-Identifier: GPL-2.0+<br>
+ */<br>
+#ifndef __AST_I2C_H_<br>
+#define __AST_I2C_H_<br>
+<br>
+struct ast_i2c_regs {<br>
+ uint32_t fcr;<br>
+ uint32_t cactcr1;<br>
+ uint32_t cactcr2;<br>
+ uint32_t icr;<br>
+ uint32_t isr;<br>
+ uint32_t csr;<br>
+ uint32_t sdar;<br>
+ uint32_t pbcr;<br>
+ uint32_t trbbr;<br>
+#ifdef CONFIG_TARGET_AST_G5<br>
+ uint32_t dma_mbar;<br>
+ uint32_t dma_tlr;<br>
+#endif<br>
+};<br>
+<br>
+/* Device Register Definition */<br>
+/* 0x00 : I2CD Function Control Register */<br>
+#define AST_I2CD_BUFF_SEL_MASK (0x7 << 20)<br>
+#define AST_I2CD_BUFF_SEL(x) (x << 20) // page 0 ~ 7<br>
+#define AST_I2CD_M_SDA_LOCK_EN (0x1 << 16)<br>
+#define AST_I2CD_MULTI_MASTER_DIS (0x1 << 15)<br>
+#define AST_I2CD_M_SCL_DRIVE_EN (0x1 << 14)<br>
+#define AST_I2CD_MSB_STS (0x1 << 9)<br>
+#define AST_I2CD_SDA_DRIVE_1T_EN (0x1 << 8)<br>
+#define AST_I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7)<br>
+#define AST_I2CD_M_HIGH_SPEED_EN (0x1 << 6)<br>
+#define AST_I2CD_DEF_ADDR_EN (0x1 << 5)<br>
+#define AST_I2CD_DEF_ALERT_EN (0x1 << 4)<br>
+#define AST_I2CD_DEF_ARP_EN (0x1 << 3)<br>
+#define AST_I2CD_DEF_GCALL_EN (0x1 << 2)<br>
+#define AST_I2CD_SLAVE_EN (0x1 << 1)<br>
+#define AST_I2CD_MASTER_EN (0x1 )<br>
+<br>
+/* 0x04 : I2CD Clock and AC Timing Control Register #1 */<br>
+#define AST_I2CD_tBUF (0x1 << 28) // 0~7<br>
+#define AST_I2CD_tHDSTA (0x1 << 24) // 0~7<br>
+#define AST_I2CD_tACST (0x1 << 20) // 0~7<br>
+#define AST_I2CD_tCKHIGH (0x1 << 16) // 0~7<br>
+#define AST_I2CD_tCKLOW (0x1 << 12) // 0~7<br>
+#define AST_I2CD_tHDDAT (0x1 << 10) // 0~7<br>
+#define AST_I2CD_CLK_TO_BASE_DIV (0x1 << 8) // 0~3<br>
+#define AST_I2CD_CLK_BASE_DIV (0x1 ) // 0~0xf<br>
+<br>
+/* 0x08 : I2CD Clock and AC Timing Control Register #2 */<br>
+#define AST_I2CD_tTIMEOUT (0x1 ) // 0~7<br>
+#define AST_NO_TIMEOUT_CTRL 0x0<br>
+<br>
+/* 0x0c : I2CD Interrupt Control Register &<br>
+ * 0x10 : I2CD Interrupt Status Register<br>
+ *<br>
+ * These share bit definitions, so use the same values for the enable &<br>
+ * status bits.<br>
+ */<br>
+#define AST_I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14)<br>
+#define AST_I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13)<br>
+#define AST_I2CD_INTR_SMBUS_ALERT (0x1 << 12)<br>
+#define AST_I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11)<br>
+#define AST_I2CD_INTR_SMBUS_DEV_ALERT_<wbr>ADDR (0x1 << 10)<br>
+#define AST_I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9)<br>
+#define AST_I2CD_INTR_GCALL_ADDR (0x1 << 8)<br>
+#define AST_I2CD_INTR_SLAVE_MATCH (0x1 << 7)<br>
+#define AST_I2CD_INTR_SCL_TIMEOUT (0x1 << 6)<br>
+#define AST_I2CD_INTR_ABNORMAL (0x1 << 5)<br>
+#define AST_I2CD_INTR_NORMAL_STOP (0x1 << 4)<br>
+#define AST_I2CD_INTR_ARBIT_LOSS (0x1 << 3)<br>
+#define AST_I2CD_INTR_RX_DONE (0x1 << 2)<br>
+#define AST_I2CD_INTR_TX_NAK (0x1 << 1)<br>
+#define AST_I2CD_INTR_TX_ACK (0x1 << 0)<br>
+<br>
+/* 0x14 : I2CD Command/Status Register */<br>
+#define AST_I2CD_SDA_OE (0x1 << 28)<br>
+#define AST_I2CD_SDA_O (0x1 << 27)<br>
+#define AST_I2CD_SCL_OE (0x1 << 26)<br>
+#define AST_I2CD_SCL_O (0x1 << 25)<br>
+#define AST_I2CD_TX_TIMING (0x1 << 24) // 0 ~3<br>
+#define AST_I2CD_TX_STATUS (0x1 << 23)<br>
+<br>
+// Tx State Machine<br>
+#define AST_I2CD_IDLE 0x0<br>
+#define AST_I2CD_MACTIVE 0x8<br>
+#define AST_I2CD_MSTART 0x9<br>
+#define AST_I2CD_MSTARTR 0xa<br>
+#define AST_I2CD_MSTOP 0xb<br>
+#define AST_I2CD_MTXD 0xc<br>
+#define AST_I2CD_MRXACK 0xd<br>
+#define AST_I2CD_MRXD 0xe<br>
+#define AST_I2CD_MTXACK 0xf<br>
+#define AST_I2CD_SWAIT 0x1<br>
+#define AST_I2CD_SRXD 0x4<br>
+#define AST_I2CD_STXACK 0x5<br>
+#define AST_I2CD_STXD 0x6<br>
+#define AST_I2CD_SRXACK 0x7<br>
+#define AST_I2CD_RECOVER 0x3<br>
+<br>
+#define AST_I2CD_SCL_LINE_STS (0x1 << 18)<br>
+#define AST_I2CD_SDA_LINE_STS (0x1 << 17)<br>
+#define AST_I2CD_BUS_BUSY_STS (0x1 << 16)<br>
+#define AST_I2CD_SDA_OE_OUT_DIR (0x1 << 15)<br>
+#define AST_I2CD_SDA_O_OUT_DIR (0x1 << 14)<br>
+#define AST_I2CD_SCL_OE_OUT_DIR (0x1 << 13)<br>
+#define AST_I2CD_SCL_O_OUT_DIR (0x1 << 12)<br>
+#define AST_I2CD_BUS_RECOVER_CMD (0x1 << 11)<br>
+#define AST_I2CD_S_ALT_EN (0x1 << 10)<br>
+// 0 : DMA Buffer, 1: Pool Buffer<br>
+//AST1070 DMA register<br>
+#define AST_I2CD_RX_DMA_ENABLE (0x1 << 9)<br>
+#define AST_I2CD_TX_DMA_ENABLE (0x1 << 8)<br>
+<br>
+/* Command Bit */<br>
+#define AST_I2CD_RX_BUFF_ENABLE (0x1 << 7)<br>
+#define AST_I2CD_TX_BUFF_ENABLE (0x1 << 6)<br>
+#define AST_I2CD_M_STOP_CMD (0x1 << 5)<br>
+#define AST_I2CD_M_S_RX_CMD_LAST (0x1 << 4)<br>
+#define AST_I2CD_M_RX_CMD (0x1 << 3)<br>
+#define AST_I2CD_S_TX_CMD (0x1 << 2)<br>
+#define AST_I2CD_M_TX_CMD (0x1 << 1)<br>
+#define AST_I2CD_M_START_CMD (0x1 )<br>
+<br>
+/* 0x18 : I2CD Slave Device Address Register */<br>
+<br>
+/* 0x1C : I2CD Pool Buffer Control Register */<br>
+#define AST_I2CD_RX_BUF_ADDR_GET(x) (((x) >> 24) & 0xff)<br>
+#define AST_I2CD_RX_BUF_END_ADDR_SET(<wbr>x) ((x) << 16)<br>
+#define AST_I2CD_TX_DATA_BUF_END_SET(<wbr>x) (((x) & 0xff) << 8)<br>
+#define AST_I2CD_RX_DATA_BUF_GET(x) (((x) >> 8) & 0xff)<br>
+#define AST_I2CD_BUF_BASE_ADDR_SET(x) ((x) & 0x3f)<br>
+<br>
+/* 0x20 : I2CD Transmit/Receive Byte Buffer Register */<br>
+#define AST_I2CD_GET_MODE(x) (((x) >> 8) & 0x1)<br>
+<br>
+#define AST_I2CD_RX_BYTE_BUFFER (0xff << 8)<br>
+#define AST_I2CD_TX_BYTE_BUFFER (0xff )<br>
+<br>
+//1. usage flag , 2 size, 3. request address<br>
+/* Use platform_data instead of module parameters */<br>
+/* Fast Mode = 400 kHz, Standard = 100 kHz */<br>
+//static int clock = 100; /* Default: 100 kHz */<br>
+<br>
+#define AST_I2CD_CMDS (AST_I2CD_BUS_RECOVER_CMD_EN | \<br>
+ AST_I2CD_M_STOP_CMD | \<br>
+ AST_I2CD_M_S_RX_CMD_LAST | \<br>
+ AST_I2CD_M_RX_CMD | \<br>
+ AST_I2CD_M_TX_CMD | \<br>
+ AST_I2CD_M_START_CMD)<br>
+<br>
+#endif /* _ASPEED_REGS_I2C_H_ */<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.8.0.rc3.226.g39d4020<br>
<br>
</font></span></blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature" data-smartmail="gmail_signature"><div><b>M</b>axim <b>S</b>loyko</div></div>
</div>