<div dir="ltr">Ping!</div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Sep 2, 2016 at 10:58 AM, <span dir="ltr"><<a href="mailto:maxims@google.com" target="_blank">maxims@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Maxim Sloyko <<a href="mailto:maxims@google.com">maxims@google.com</a>><br>
<br>
Set up a stack in SRAM at the beginning of lowlevel_init, which makes it<br>
possible to call non-trivial C functions, as well as put diagnostic<br>
strings themselves onto the stack.<br>
<br>
Several one-char writes to debug uart still remain in platform.S, I<br>
figured it's not worth it to make a separate call to c function for each<br>
of those.<br>
---<br>
arch/arm/include/asm/arch-<wbr>aspeed/ast_uart.h | 142 +++++++++++<br>
arch/arm/include/asm/arch-<wbr>aspeed/regs-scu.h | 4 +-<br>
arch/arm/mach-aspeed/Makefile | 2 +-<br>
arch/arm/mach-aspeed/ast_uart.<wbr>c | 38 +++<br>
board/aspeed/ast-g5/ast-g5.c | 110 ++++++++-<br>
board/aspeed/ast-g5/platform.S | 351 +++-------------------------<br>
6 files changed, 318 insertions(+), 329 deletions(-)<br>
create mode 100644 arch/arm/include/asm/arch-<wbr>aspeed/ast_uart.h<br>
create mode 100644 arch/arm/mach-aspeed/ast_uart.<wbr>c<br>
<br>
diff --git a/arch/arm/include/asm/arch-<wbr>aspeed/ast_uart.h b/arch/arm/include/asm/arch-<wbr>aspeed/ast_uart.h<br>
new file mode 100644<br>
index 0000000..ddf1a14<br>
--- /dev/null<br>
+++ b/arch/arm/include/asm/arch-<wbr>aspeed/ast_uart.h<br>
@@ -0,0 +1,142 @@<br>
+/****************************<wbr>******************************<wbr>*********************<br>
+ * Copyright (C) 2016 Google Inc<br>
+ *<br>
+ * This program is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU General Public License as<br>
+ * published by the Free Software Foundation; either version 2 of the<br>
+ * License, or (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful, but<br>
+ * WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU<br>
+ * General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307<br>
+ * USA<br>
+ ******************************<wbr>******************************<wbr>******************/<br>
+<br>
+#ifndef __AST_UART_H<br>
+#define __AST_UART_H<br>
+<br>
+#include <asm/io.h><br>
+<br>
+#define AST_UART_RBR(uart) (uart)<br>
+#define AST_UART_THR(uart) (uart)<br>
+#define AST_UART_IER(uart) ((uart) + 0x4)<br>
+#define AST_UART_IIR(uart) ((uart) + 0x8)<br>
+#define AST_UART_FCR(uart) ((uart) + 0x8)<br>
+#define AST_UART_LCR(uart) ((uart) + 0xc)<br>
+#define AST_UART_MCR(uart) ((uart) + 0x10)<br>
+#define AST_UART_LSR(uart) ((uart) + 0x14)<br>
+#define AST_UART_MSR(uart) ((uart) + 0x18)<br>
+#define AST_UART_SCR(uart) ((uart) + 0x1c)<br>
+<br>
+/* These registers can only be written when DLAB = 1*/<br>
+#define AST_UART_DLL(uart) ((uart))<br>
+#define AST_UART_DLH(uart) ((uart) + 0x4)<br>
+<br>
+/* Registers' contents */<br>
+<br>
+#define AST_UART_IER_THRE (1 << 7)<br>
+#define AST_UART_IER_EDSSI (1 << 3)<br>
+#define AST_UART_IER_ELSI (1 << 2)<br>
+#define AST_UART_IER_ETBEI (1 << 1)<br>
+#define AST_UART_IER_ERBFI (1 << 0)<br>
+<br>
+/* AND this mask with AST_UART_IIR to find out if FIFOs are enabled. */<br>
+#define AST_UART_IIR_FEN_MASK (3 << 6)<br>
+<br>
+/* Bit0 == 0 means that the interrupt is pending, bits 3:1 identify<br>
+ * interrupt. These values are defined so that IIR | 0xf would give you the<br>
+ * value for the interrupt. */<br>
+#define AST_UART_IIR_MSC (0)<br>
+#define AST_UART_IIR_THRE (1 << 1)<br>
+#define AST_UART_IIR_RDA (2 << 1)<br>
+#define AST_UART_IIR_RS (3 << 1)<br>
+#define AST_UART_IIR_CTO (6 << 1)<br>
+<br>
+/* RX FIFO Interrupt trigger level */<br>
+#define AST_UART_FCR_RXFITL_MASK (3 << 6)<br>
+/* One byte received */<br>
+#define AST_UART_FCR_RXFITL1 (0)<br>
+/* 4 bytes received */<br>
+#define AST_UART_FCR_RXFITL4 (1 << 6)<br>
+/* 8 bytes received */<br>
+#define AST_UART_FCR_RXFITL8 (2 << 6)<br>
+/* 14 bytes received */<br>
+#define AST_UART_FCR_RXFITL14 (3 << 6)<br>
+<br>
+/* TX FIFO Interrupt trigger level */<br>
+#define AST_UART_FCR_TXFITL_MASK (3 << 4)<br>
+/* FIFO Empty (0 bytes in FIFO) */<br>
+#define AST_UART_FCR_TXFITL0 (0)<br>
+/* 2 bytes in FIFO */<br>
+#define AST_UART_FCR_TXFITL2 (1 << 4)<br>
+/* FIFO 1/4 full (4 bytes) */<br>
+#define AST_UART_FCR_TXFITLQ (2 << 4)<br>
+/* FIFO 1/2 full (8 bytes) */<br>
+#define AST_UART_FCR_TXFITLH (3 << 4)<br>
+<br>
+#define AST_UART_FCR_TXFRST (1 << 2)<br>
+#define AST_UART_FCR_RXFRST (1 << 1)<br>
+#define AST_UART_FCR_FEN (1 << 0)<br>
+<br>
+#define AST_UART_LCR_DLAB (1 << 7)<br>
+#define AST_UART_LCR_BC (1 << 6)<br>
+#define AST_UART_LCR_EPS (1 << 4)<br>
+#define AST_UART_LCR_PEN (1 << 3)<br>
+#define AST_UART_LCR_STOP (1 << 2)<br>
+<br>
+/* Number of bits per character */<br>
+#define AST_UART_LCR_BPC_MASK (3)<br>
+#define AST_UART_LCR_BPC5 (0)<br>
+#define AST_UART_LCR_BPC6 (1)<br>
+#define AST_UART_LCR_BPC7 (2)<br>
+#define AST_UART_LCR_BPC8 (3)<br>
+<br>
+#define AST_UART_MCR_LB (1 << 4)<br>
+#define AST_UART_MCR_OUT2 (1 << 3)<br>
+#define AST_UART_MCR_OUT1 (1 << 2)<br>
+#define AST_UART_MCR_RTS (1 << 1)<br>
+#define AST_UART_MCR_DTR (1 << 0)<br>
+<br>
+#define AST_UART_LSR_ERXF (1 << 7)<br>
+#define AST_UART_LSR_TEMPTY (1 << 6)<br>
+#define AST_UART_LSR_THRE (1 << 5)<br>
+#define AST_UART_LSR_BI (1 << 4)<br>
+#define AST_UART_LSR_FE (1 << 3)<br>
+#define AST_UART_LSR_PE (1 << 2)<br>
+#define AST_UART_LSR_OE (1 << 1)<br>
+#define AST_UART_LSR_DR (1 << 0)<br>
+<br>
+#define AST_UART_MSR_NDCD_OUT2 (1 << 7)<br>
+#define AST_UART_MSR_NRI_OUT1 (1 << 6)<br>
+#define AST_UART_MSR_NDSR_NDTR (1 << 5)<br>
+#define AST_UART_MSR_NCTS_NRTS (1 << 4)<br>
+#define AST_UART_MSR_DDCD (1 << 3)<br>
+#define AST_UART_MSR_TERI (1 << 2)<br>
+#define AST_UART_MSR_DDSR (1 << 1)<br>
+#define AST_UART_MSR_DCTS (1 << 0)<br>
+<br>
+#define AST_UART_FIFO_SIZE (16)<br>
+<br>
+#define ast_uart_wait_txempty(uart) while(!(readl(AST_UART_LSR((<wbr>uart))) & AST_UART_LSR_TEMPTY))<br>
+#define ast_uart_write(uart, c) writel((c), AST_UART_THR((uart)))<br>
+#define ast_uart_enable_fifo(uart) setbits_le32(AST_UART_FCR((<wbr>uart)), AST_UART_FCR_FEN)<br>
+#define ast_uart_enable_thre_mode(<wbr>uart) setbits_le32(AST_UART_IER(<wbr>uart), AST_UART_IER_THRE)<br>
+<br>
+/* In THRE and FIFO mode, wait until there is some space in FIFO */<br>
+#define ast_uart_wait_fifo_ready(uart) while((readl(AST_UART_LSR(<wbr>uart)) & AST_UART_LSR_THRE))<br>
+<br>
+#define ast_uart_set_bpc(uart, bpc) clrsetbits_le32(AST_UART_LCR((<wbr>uart)), AST_UART_LCR_BPC_MASK, (bpc))<br>
+<br>
+#define ast_uart_unlock_dlab(uart) setbits_le32(AST_UART_LCR((<wbr>uart)), AST_UART_LCR_DLAB)<br>
+#define ast_uart_lock_dlab(uart) clrbits_le32(AST_UART_LCR(<wbr>uart), AST_UART_LCR_DLAB)<br>
+<br>
+/* NOTE: These write functions only work when THRE mode and FIFOs are enabled. */<br>
+void ast_uart_write_buffer_sync(<wbr>uint32_t uart, const uint8_t* buffer, uint16_t len);<br>
+void ast_uart_write_string_sync(<wbr>uint32_t uart, const char* s);<br>
+<br>
+#endif<br>
diff --git a/arch/arm/include/asm/arch-<wbr>aspeed/regs-scu.h b/arch/arm/include/asm/arch-<wbr>aspeed/regs-scu.h<br>
index b89df82..b714fa9 100644<br>
--- a/arch/arm/include/asm/arch-<wbr>aspeed/regs-scu.h<br>
+++ b/arch/arm/include/asm/arch-<wbr>aspeed/regs-scu.h<br>
@@ -10,8 +10,8 @@<br>
* 1. 2012/12/29 Ryan Chen Create<br>
*<br>
******************************<wbr>******************************<wbr>********************/<br>
-#ifndef __AST_SCU_H<br>
-#define __AST_SCU_H 1<br>
+#ifndef __AST_REGS_SCU_H<br>
+#define __AST_REGS_SCU_H 1<br>
<br>
#include <asm/arch/aspeed.h><br>
<br>
diff --git a/arch/arm/mach-aspeed/<wbr>Makefile b/arch/arm/mach-aspeed/<wbr>Makefile<br>
index d72f62a..3e0b4f7 100644<br>
--- a/arch/arm/mach-aspeed/<wbr>Makefile<br>
+++ b/arch/arm/mach-aspeed/<wbr>Makefile<br>
@@ -11,5 +11,5 @@<br>
#<br>
<br>
<br>
-obj-y += timer.o reset.o cpuinfo.o ast-scu.o ast-ahbc.o ast-sdmc.o<br>
+obj-y += timer.o reset.o cpuinfo.o ast-scu.o ast-ahbc.o ast-sdmc.o ast_uart.o<br>
obj-$(CONFIG_AST_SPI_NOR) += flash.o<br>
diff --git a/arch/arm/mach-aspeed/ast_<wbr>uart.c b/arch/arm/mach-aspeed/ast_<wbr>uart.c<br>
new file mode 100644<br>
index 0000000..1226827<br>
--- /dev/null<br>
+++ b/arch/arm/mach-aspeed/ast_<wbr>uart.c<br>
@@ -0,0 +1,38 @@<br>
+/****************************<wbr>******************************<wbr>*********************<br>
+ * Copyright (C) 2016 Google Inc<br>
+ *<br>
+ * This program is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU General Public License as<br>
+ * published by the Free Software Foundation; either version 2 of the<br>
+ * License, or (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful, but<br>
+ * WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU<br>
+ * General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307<br>
+ * USA<br>
+ ******************************<wbr>******************************<wbr>******************/<br>
+<br>
+#include <asm/io.h><br>
+#include <asm/arch/ast_uart.h><br>
+<br>
+void ast_uart_write_buffer_sync(<wbr>uint32_t uart, const uint8_t *buffer,<br>
+ uint16_t len)<br>
+{<br>
+ for (; len; --len, ++buffer) {<br>
+ ast_uart_wait_fifo_ready(uart)<wbr>;<br>
+ ast_uart_write(uart, *buffer);<br>
+ }<br>
+}<br>
+<br>
+void ast_uart_write_string_sync(<wbr>uint32_t uart, const char *s)<br>
+{<br>
+ for (; *s; ++s) {<br>
+ ast_uart_wait_fifo_ready(uart)<wbr>;<br>
+ ast_uart_write(uart, *s);<br>
+ }<br>
+}<br>
diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c<br>
index 81ea88a..b0b8535 100644<br>
--- a/board/aspeed/ast-g5/ast-g5.c<br>
+++ b/board/aspeed/ast-g5/ast-g5.c<br>
@@ -35,16 +35,21 @@<br>
<br>
#include <common.h><br>
#include <netdev.h><br>
-#include <asm/arch/ast_scu.h><br>
+#include <asm/arch/ast_g5_platform.h><br>
#include <asm/arch/ast-sdmc.h><br>
+#include <asm/arch/ast_scu.h><br>
+#include <asm/arch/ast_uart.h><br>
+#include <asm/arch/regs-scu.h><br>
#include <asm/io.h><br>
<br>
+#define AST_DEBUG_UART (0x1e784000)<br>
+<br>
DECLARE_GLOBAL_DATA_PTR;<br>
<br>
#if defined(CONFIG_SHOW_BOOT_<wbr>PROGRESS)<br>
void show_boot_progress(int progress)<br>
{<br>
- printf("Boot reached stage %d\n", progress);<br>
+ printf("Boot reached stage %d\n", progress);<br>
}<br>
#endif<br>
<br>
@@ -66,9 +71,108 @@ int dram_init(void)<br>
return 0;<br>
}<br>
<br>
+/* assumes digit < 16 */<br>
+static inline char hex_digit(uint8_t digit)<br>
+{<br>
+ if (digit < 10) {<br>
+ return '0' + digit;<br>
+ } else {<br>
+ return 'a' + (digit - 10);<br>
+ }<br>
+}<br>
+<br>
+static inline void format_u8_hex(char *dst, uint8_t value)<br>
+{<br>
+ *dst = hex_digit(value >> 4);<br>
+ *(dst + 1) = hex_digit(value & 0xf);<br>
+}<br>
+<br>
+static inline void debug_uart_print(const char *s)<br>
+{<br>
+ ast_uart_write_string_sync(<wbr>AST_DEBUG_UART, s);<br>
+}<br>
+<br>
+void debug_print_ddr_version(uint8_<wbr>t version)<br>
+{<br>
+ char message[8] = "-DDR_\r\n";<br>
+ message[4] = '0' + version;<br>
+ debug_uart_print(message);<br>
+}<br>
+<br>
+void debug_print_dram_init_message(<wbr>uint8_t version)<br>
+{<br>
+ char message[16] = "\r\nDRAM Init-V__";<br>
+ char *version_dst = message + 13;<br>
+ format_u8_hex(version_dst, version);<br>
+ debug_uart_print(message);<br>
+}<br>
+<br>
+void debug_print_dram_size(char size)<br>
+{<br>
+ char message[6] = "-_Gb-";<br>
+ message[1] = size;<br>
+ debug_uart_print(message);<br>
+}<br>
+<br>
+void debug_print_ddr_status(bool done)<br>
+{<br>
+ if (done) {<br>
+ debug_uart_print("Done\r\n");<br>
+ } else {<br>
+ debug_uart_print("Fail\r\n");<br>
+ }<br>
+}<br>
+<br>
+static inline void format_phy_timing(char *dst, uint8_t value)<br>
+{<br>
+ /* This is adopted from platforms.S file by Aspeed.<br>
+ * They read memory address (which is not mentioned in the data sheet)<br>
+ * and then divide byte value by 510 and print 4 digits after the dot.<br>
+ */<br>
+ uint32_t timing_value = value * 1000 / 51;<br>
+ for (int index = 3; index >= 0 && timing_value > 0; --index) {<br>
+ uint8_t digit = timing_value % 10;<br>
+ timing_value /= 10;<br>
+ dst[index] = '0' + digit;<br>
+ }<br>
+}<br>
+<br>
+void debug_print_ddr_phy_timing(<wbr>uint16_t margin)<br>
+{<br>
+ char message[46] = "Read margin DL:0.0000/0.0000 CK (min: 0.35)\r\n";<br>
+ format_phy_timing(message + 17, margin & 0xff);<br>
+ format_phy_timing(message + 24, (margin >> 8) & 0xff);<br>
+ debug_uart_print(message);<br>
+}<br>
+<br>
+static void init_uart_for_debug(uint32_t uart_base)<br>
+{<br>
+ ast_uart_set_bpc(uart_base, AST_UART_LCR_BPC8);<br>
+ ast_uart_unlock_dlab(uart_<wbr>base);<br>
+ const uint32_t uart_clk_mul =<br>
+ readl(AST_SCU_BASE + AST_SCU_MISC1_CTRL) & (1 << 12) ? 1 : 13;<br>
+#ifdef CONFIG_DRAM_UART_38400<br>
+ const uint32_t br_base = 3 * uart_clk_mul;<br>
+#else<br>
+ const uint32_t br_base = 1 * uart_clk_mul;<br>
+#endif<br>
+ writel(br_base, AST_UART_DLL(uart_base));<br>
+ writel(0, AST_UART_DLH(uart_base));<br>
+<br>
+ /* Lock DLAB */<br>
+ ast_uart_lock_dlab(uart_base);<br>
+ ast_uart_enable_fifo(uart_<wbr>base);<br>
+ ast_uart_enable_thre_mode(<wbr>uart_base);<br>
+}<br>
+<br>
+void init_debug_uart(void)<br>
+{<br>
+ init_uart_for_debug(AST_DEBUG_<wbr>UART);<br>
+}<br>
+<br>
#ifdef CONFIG_CMD_NET<br>
int board_eth_init(bd_t *bd)<br>
{<br>
- return ftgmac100_initialize(bd);<br>
+ return ftgmac100_initialize(bd);<br>
}<br>
#endif<br>
diff --git a/board/aspeed/ast-g5/<wbr>platform.S b/board/aspeed/ast-g5/<wbr>platform.S<br>
index c810f44..a33afee 100644<br>
--- a/board/aspeed/ast-g5/<wbr>platform.S<br>
+++ b/board/aspeed/ast-g5/<wbr>platform.S<br>
@@ -78,7 +78,6 @@<br>
#include <version.h><br>
<br>
/*****************************<wbr>******************************<wbr>*******************<br>
- r4 : return program counter<br>
r5 : DDR speed timing table base address<br>
Free registers:<br>
r0, r1, r2, r3, r6, r7, r8, r9, r10, r11<br>
@@ -104,6 +103,9 @@<br>
#define ASTMMC_REGIDX_RFC 0x3C<br>
#define ASTMMC_REGIDX_PLL 0x40<br>
<br>
+#define AST_SRAM_END 0x1e728ffc<br>
+<br>
+<br>
TIME_TABLE_DDR3_1333:<br>
.word 0x53503C37 @ 0x010<br>
.word 0xF858D47F @ 0x014<br>
@@ -242,12 +244,20 @@ TIME_TABLE_DDR4_1600:<br>
Calibration Macro End<br>
******************************<wbr>******************************<wbr>******************/<br>
<br>
+.globl debug_print_dram_init_message<br>
+.globl debug_print_ddr_version<br>
+.globl debug_print_dram_size<br>
+.globl debug_print_ddr_status<br>
+.globl debug_print_ddr_phy_timing<br>
+.globl init_debug_uart<br>
.globl lowlevel_init<br>
lowlevel_init:<br>
<br>
init_dram:<br>
+ /* Setup a stack in SRAM */<br>
+ ldr sp, =AST_SRAM_END<br>
/* save lr */<br>
- mov r4, lr<br>
+ push {lr}<br>
<br>
/* Clear AHB bus lock condition */<br>
ldr r0, =0x1e600000<br>
@@ -489,82 +499,10 @@ wait_mmc_reset_done:<br>
ldr r1, =0x00020000<br>
str r1, [r0]<br>
<br>
-/* Debug - UART console message */<br>
- ldr r0, =0x1e78400c<br>
- mov r1, #0x83<br>
- str r1, [r0]<br>
-<br>
- ldr r0, =0x1e6e202c<br>
- ldr r2, [r0]<br>
- mov r2, r2, lsr #12<br>
- tst r2, #0x01<br>
- ldr r0, =0x1e784000<br>
- moveq r1, #0x0D @ Baudrate 115200<br>
- movne r1, #0x01 @ Baudrate 115200, div13<br>
-#ifdef CONFIG_DRAM_UART_38400<br>
- moveq r1, #0x27 @ Baudrate 38400<br>
- movne r1, #0x03 @ Baudrate 38400 , div13<br>
-#endif<br>
- str r1, [r0]<br>
-<br>
- ldr r0, =0x1e784004<br>
- mov r1, #0x00<br>
- str r1, [r0]<br>
-<br>
- ldr r0, =0x1e78400c<br>
- mov r1, #0x03<br>
- str r1, [r0]<br>
-<br>
- ldr r0, =0x1e784008<br>
- mov r1, #0x07<br>
- str r1, [r0]<br>
+ bl init_debug_uart<br>
<br>
- ldr r0, =0x1e784000<br>
- mov r1, #0x0D @ '\r'<br>
- str r1, [r0]<br>
- mov r1, #0x0A @ '\n'<br>
- str r1, [r0]<br>
- mov r1, #0x44 @ 'D'<br>
- str r1, [r0]<br>
- mov r1, #0x52 @ 'R'<br>
- str r1, [r0]<br>
- mov r1, #0x41 @ 'A'<br>
- str r1, [r0]<br>
- mov r1, #0x4D @ 'M'<br>
- str r1, [r0]<br>
- mov r1, #0x20 @ ' '<br>
- str r1, [r0]<br>
- mov r1, #0x49 @ 'I'<br>
- str r1, [r0]<br>
- mov r1, #0x6E @ 'n'<br>
- str r1, [r0]<br>
- mov r1, #0x69 @ 'i'<br>
- str r1, [r0]<br>
- mov r1, #0x74 @ 't'<br>
- str r1, [r0]<br>
- mov r1, #0x2D @ '-'<br>
- str r1, [r0]<br>
- mov r1, #0x56 @ 'V'<br>
- str r1, [r0]<br>
- mov r1, #ASTMMC_INIT_VER<br>
- mov r1, r1, lsr #4<br>
- print_hex_char<br>
- mov r1, #ASTMMC_INIT_VER<br>
- print_hex_char<br>
- mov r1, #0x2D @ '-'<br>
- str r1, [r0]<br>
- ldr r0, =0x1e784014<br>
-wait_print:<br>
- ldr r1, [r0]<br>
- tst r1, #0x40<br>
- beq wait_print<br>
- ldr r0, =0x1e784000<br>
- mov r1, #0x44 @ 'D'<br>
- str r1, [r0]<br>
- mov r1, #0x44 @ 'D'<br>
- str r1, [r0]<br>
- mov r1, #0x52 @ 'R'<br>
- str r1, [r0]<br>
+ mov r0, #ASTMMC_INIT_VER<br>
+ bl debug_print_dram_init_message<br>
/* Debug - UART console message */<br>
<br>
/*****************************<wbr>******************************<wbr>*******************<br>
@@ -647,15 +585,8 @@ wait_print:<br>
DDR3 Init<br>
******************************<wbr>******************************<wbr>******************/<br>
ddr3_init:<br>
-/* Debug - UART console message */<br>
- ldr r0, =0x1e784000<br>
- mov r1, #0x33 @ '3'<br>
- str r1, [r0]<br>
- mov r1, #0x0D @ '\r'<br>
- str r1, [r0]<br>
- mov r1, #0x0A @ '\n'<br>
- str r1, [r0]<br>
-/* Debug - UART console message */<br>
+ mov r0, #3<br>
+ bl debug_print_ddr_version<br>
<br>
#if defined (CONFIG_DRAM_1333)<br>
adrl r5, TIME_TABLE_DDR3_1333 @ Init DRAM parameter table<br>
@@ -865,15 +796,8 @@ ddr3_check_dllrdy:<br>
DDR4 Init<br>
******************************<wbr>******************************<wbr>******************/<br>
ddr4_init:<br>
-/* Debug - UART console message */<br>
- ldr r0, =0x1e784000<br>
- mov r1, #0x34 @ '4'<br>
- str r1, [r0]<br>
- mov r1, #0x0D @ '\r'<br>
- str r1, [r0]<br>
- mov r1, #0x0A @ '\n'<br>
- str r1, [r0]<br>
-/* Debug - UART console message */<br>
+ mov r0, #4<br>
+ bl debug_print_ddr_version<br>
<br>
#if defined (CONFIG_DRAM_1333)<br>
adrl r5, TIME_TABLE_DDR4_1333 @ Init DRAM parameter table<br>
@@ -1439,18 +1363,8 @@ check_dram_size_end:<br>
ldr r1, =ASTMMC_INIT_DATE<br>
str r1, [r0]<br>
<br>
-/* Debug - UART console message */<br>
- ldr r0, =0x1e784000<br>
- mov r1, #0x2D @ '-'<br>
- str r1, [r0]<br>
- str r3, [r0]<br>
- mov r1, #0x47 @ 'G'<br>
- str r1, [r0]<br>
- mov r1, #0x62 @ 'b'<br>
- str r1, [r0]<br>
- mov r1, #0x2D @ '-'<br>
- str r1, [r0]<br>
-/* Debug - UART console message */<br>
+ mov r0, r3<br>
+ bl debug_print_dram_size<br>
<br>
/* Enable DRAM Cache */<br>
ldr r0, =0x1e6e0004<br>
@@ -1520,26 +1434,8 @@ ddr_wait_engine_idle_1:<br>
b set_scratch @ CBRTest() return(1)<br>
<br>
ddr_test_fail:<br>
-/* Debug - UART console message */<br>
- ldr r0, =0x1e784000<br>
- mov r1, #0x46 @ 'F'<br>
- str r1, [r0]<br>
- mov r1, #0x61 @ 'a'<br>
- str r1, [r0]<br>
- mov r1, #0x69 @ 'i'<br>
- str r1, [r0]<br>
- mov r1, #0x6C @ 'l'<br>
- str r1, [r0]<br>
- mov r1, #0x0D @ '\r'<br>
- str r1, [r0]<br>
- mov r1, #0x0A @ '\n'<br>
- str r1, [r0]<br>
- ldr r0, =0x1e784014<br>
-wait_print_0:<br>
- ldr r1, [r0]<br>
- tst r1, #0x40<br>
- beq wait_print_0<br>
-/* Debug - UART console message */<br>
+ mov r0, #0<br>
+ bl debug_print_ddr_status<br>
b reset_mmc<br>
<br>
set_scratch:<br>
@@ -1549,21 +1445,8 @@ set_scratch:<br>
orr r1, r1, #0x41<br>
str r1, [r0]<br>
<br>
-/* Debug - UART console message */<br>
- ldr r0, =0x1e784000<br>
- mov r1, #0x44 @ 'D'<br>
- str r1, [r0]<br>
- mov r1, #0x6F @ 'o'<br>
- str r1, [r0]<br>
- mov r1, #0x6E @ 'n'<br>
- str r1, [r0]<br>
- mov r1, #0x65 @ 'e'<br>
- str r1, [r0]<br>
- mov r1, #0x0D @ '\r'<br>
- str r1, [r0]<br>
- mov r1, #0x0A @ '\n'<br>
- str r1, [r0]<br>
-/* Debug - UART console message */<br>
+ mov r0, #1<br>
+ bl debug_print_ddr_status<br>
<br>
/* Enable VGA display */<br>
ldr r0, =0x1e6e202c<br>
@@ -1571,184 +1454,10 @@ set_scratch:<br>
bic r1, r1, #0x40<br>
str r1, [r0]<br>
<br>
-/* Debug - UART console message */<br>
- /* Print PHY timing information */<br>
- ldr r0, =0x1e784014<br>
-wait_print_1:<br>
- ldr r1, [r0]<br>
- tst r1, #0x40<br>
- beq wait_print_1<br>
-<br>
- ldr r0, =0x1e784000<br>
- mov r1, #0x52 @ 'R'<br>
- str r1, [r0]<br>
- mov r1, #0x65 @ 'e'<br>
- str r1, [r0]<br>
- mov r1, #0x61 @ 'a'<br>
- str r1, [r0]<br>
- mov r1, #0x64 @ 'd'<br>
- str r1, [r0]<br>
- mov r1, #0x20 @ ' '<br>
- str r1, [r0]<br>
- mov r1, #0x6D @ 'm'<br>
- str r1, [r0]<br>
- mov r1, #0x61 @ 'a'<br>
- str r1, [r0]<br>
- mov r1, #0x72 @ 'r'<br>
- str r1, [r0]<br>
- mov r1, #0x67 @ 'g'<br>
- str r1, [r0]<br>
- mov r1, #0x69 @ 'i'<br>
- str r1, [r0]<br>
- mov r1, #0x6E @ 'n'<br>
- str r1, [r0]<br>
- mov r1, #0x2D @ '-'<br>
- str r1, [r0]<br>
- mov r1, #0x44 @ 'D'<br>
- str r1, [r0]<br>
- mov r1, #0x4C @ 'L'<br>
- str r1, [r0]<br>
- mov r1, #0x3A @ ':'<br>
- str r1, [r0]<br>
-<br>
- ldr r0, =0x1e784014<br>
-wait_print_2:<br>
- ldr r1, [r0]<br>
- tst r1, #0x40<br>
- beq wait_print_2<br>
-<br>
- ldr r7, =0x000001FE @ divide by 510<br>
- mov r8, #10 @ multiply by 10<br>
-print_DQL_eye_margin:<br>
- ldr r0, =0x1e6e03d0<br>
- ldr r2, [r0]<br>
- and r2, r2, #0xFF<br>
- ldr r0, =0x1e784000<br>
- mov r1, #0x30 @ '0'<br>
- str r1, [r0]<br>
- mov r1, #0x2E @ '.'<br>
- str r1, [r0]<br>
- mov r3, #0x4 @ print 4 digits<br>
-print_DQL_div_loop:<br>
- mul r2, r8, r2<br>
- cmp r2, r7<br>
- blt print_DQL_div_0<br>
- mov r6, #0x0<br>
-print_DQL_div_digit:<br>
- sub r2, r2, r7<br>
- add r6, r6, #0x1<br>
- cmp r2, r7<br>
- bge print_DQL_div_digit<br>
- b print_DQL_div_n<br>
-<br>
-print_DQL_div_0:<br>
- mov r1, #0x30 @ '0'<br>
- str r1, [r0]<br>
- b print_DQL_next<br>
-print_DQL_div_n:<br>
- add r1, r6, #0x30 @ print n<br>
- str r1, [r0]<br>
-print_DQL_next:<br>
- subs r3, r3, #1<br>
- beq print_DQH_eye_margin<br>
- cmp r2, #0x0<br>
- beq print_DQH_eye_margin<br>
- b print_DQL_div_loop<br>
-<br>
-print_DQH_eye_margin:<br>
- mov r1, #0x2F @ '/'<br>
- str r1, [r0]<br>
- mov r1, #0x44 @ 'D'<br>
- str r1, [r0]<br>
- mov r1, #0x48 @ 'H'<br>
- str r1, [r0]<br>
- mov r1, #0x3A @ ':'<br>
- str r1, [r0]<br>
-<br>
- ldr r0, =0x1e784014<br>
-wait_print_3:<br>
- ldr r1, [r0]<br>
- tst r1, #0x40<br>
- beq wait_print_3<br>
-<br>
ldr r0, =0x1e6e03d0<br>
ldr r2, [r0]<br>
- mov r2, r2, lsr #8<br>
- and r2, r2, #0xFF<br>
- ldr r0, =0x1e784000<br>
- mov r1, #0x30 @ '0'<br>
- str r1, [r0]<br>
- mov r1, #0x2E @ '.'<br>
- str r1, [r0]<br>
- mov r3, #0x4 @ print 4 digits<br>
-print_DQH_div_loop:<br>
- mul r2, r8, r2<br>
- cmp r2, r7<br>
- blt print_DQH_div_0<br>
- mov r6, #0x0<br>
-print_DQH_div_digit:<br>
- sub r2, r2, r7<br>
- add r6, r6, #0x1<br>
- cmp r2, r7<br>
- bge print_DQH_div_digit<br>
- b print_DQH_div_n<br>
-<br>
-print_DQH_div_0:<br>
- mov r1, #0x30 @ '0'<br>
- str r1, [r0]<br>
- b print_DQH_next<br>
-print_DQH_div_n:<br>
- add r1, r6, #0x30 @ print n<br>
- str r1, [r0]<br>
-print_DQH_next:<br>
- subs r3, r3, #1<br>
- beq print_DQ_eye_margin_last<br>
- cmp r2, #0x0<br>
- beq print_DQ_eye_margin_last<br>
- b print_DQH_div_loop<br>
-<br>
-print_DQ_eye_margin_last:<br>
- mov r1, #0x20 @ ' '<br>
- str r1, [r0]<br>
- mov r1, #0x43 @ 'C'<br>
- str r1, [r0]<br>
- mov r1, #0x4B @ 'K'<br>
- str r1, [r0]<br>
-<br>
- ldr r0, =0x1e784014<br>
-wait_print_4:<br>
- ldr r1, [r0]<br>
- tst r1, #0x40<br>
- beq wait_print_4<br>
-<br>
- ldr r0, =0x1e784000<br>
- mov r1, #0x20 @ ' '<br>
- str r1, [r0]<br>
- mov r1, #0x28 @ '('<br>
- str r1, [r0]<br>
- mov r1, #0x6D @ 'm'<br>
- str r1, [r0]<br>
- mov r1, #0x69 @ 'i'<br>
- str r1, [r0]<br>
- mov r1, #0x6E @ 'n'<br>
- str r1, [r0]<br>
- mov r1, #0x3A @ ':'<br>
- str r1, [r0]<br>
- mov r1, #0x30 @ '0'<br>
- str r1, [r0]<br>
- mov r1, #0x2E @ '.'<br>
- str r1, [r0]<br>
- mov r1, #0x33 @ '3'<br>
- str r1, [r0]<br>
- mov r1, #0x35 @ '5'<br>
- str r1, [r0]<br>
- mov r1, #0x29 @ ')'<br>
- str r1, [r0]<br>
- mov r1, #0x0D @ '\r'<br>
- str r1, [r0]<br>
- mov r1, #0x0A @ '\n'<br>
- str r1, [r0]<br>
-/* Debug - UART console message */<br>
+ mov r0, r2<br>
+ bl debug_print_ddr_phy_timing<br>
<br>
platform_exit:<br>
#ifdef CONFIG_DRAM_ECC<br>
@@ -1991,9 +1700,5 @@ set_D2PLL:<br>
ldr r1, =0xEA<br>
str r1, [r0]<br>
<br>
- /* restore lr */<br>
- mov lr, r4<br>
-<br>
/* back to arch calling code */<br>
- mov pc, lr<br>
-<br>
+ pop {pc}<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.8.0.rc3.226.g39d4020<br>
<br>
</font></span></blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature" data-smartmail="gmail_signature"><div><b>M</b>axim <b>S</b>loyko</div></div>
</div>