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On 3/6/19 4:35 AM, Nicolas Koenig wrote:<br>
<blockquote type="cite"
cite="mid:06649772-7f58-3475-867c-f11e08578622@student.ethz.ch">Hello
world,
<br>
<br>
After asking this question on another mailing list, I was
redirected to this list. I hope someone on here will be able to
help me :)
<br>
<br>
While running a few benchmarks, I noticed that the following code
(with SMT disabled) only manages about 2.25 xsadddp instr/clk
(measured via pmc6) instead of the expected 4:
<br>
<br>
loop:
<br>
.rept 12
<br>
xsadddp %vs2, %vs1, %vs1
<br>
.endr
<br>
bdnz loop
<br>
<br>
From what I can gather, the bottleneck shouldn't be the history
buffers. Since there are no long latency operations, FIN->COMP
shouldn't take more than 12 cycles (the size of the secondary HB
for FPSCR, the smallest relevant one). The primary HB and the
issue queue shouldn't overflow either, since xsadddp takes 7
cycles from issue to finish and they can accomodate 20 and 13
entries respectivly with one instruction only using one of each.
It doesn't stall on writeback ports either, because there are only
4 results in any one clock and 4 writeback ports (the decrement of
the bdnz instruction is handled in the branch slice without
involving the writeback network).
<br>
<br>
Has anyone here any idea where the bottleneck might be?
<br>
</blockquote>
<pre>Hi Nicolas,
I'm going to pass this along to some folks to investigate, but first I need to confirm:
I believe this is a POWER9 measurement, and specifically on a Talos workstation, correct?
Thanks,
Bill
</pre>
<blockquote type="cite"
cite="mid:06649772-7f58-3475-867c-f11e08578622@student.ethz.ch">
<br>
Thanks in advance
<br>
Nicolas
<br>
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</blockquote>
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