<br><br>On Thursday, May 6, 2021, Chris Packham <<a href="mailto:chris.packham@alliedtelesis.co.nz">chris.packham@alliedtelesis.co.nz</a>> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">The P2040/P2041 has an erratum where the normal i2c recovery mechanism<br>
does not work. Implement the alternative recovery mechanism documented<br>
in the P2040 Chip Errata Rev Q.<br>
<br>
Signed-off-by: Chris Packham <<a href="mailto:chris.packham@alliedtelesis.co.nz">chris.packham@alliedtelesis.<wbr>co.nz</a>><br>
---<br>
 drivers/i2c/busses/i2c-mpc.c | 88 ++++++++++++++++++++++++++++++<wbr>+++++-<br>
 1 file changed, 86 insertions(+), 2 deletions(-)<br>
<br>
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c<br>
index 30d9e89a3db2..052e37718771 100644<br>
--- a/drivers/i2c/busses/i2c-mpc.c<br>
+++ b/drivers/i2c/busses/i2c-mpc.c<br>
@@ -45,6 +45,7 @@<br>
 #define CCR_MTX  0x10<br>
 #define CCR_TXAK 0x08<br>
 #define CCR_RSTA 0x04<br>
+#define CCR_RSVD 0x02<br>
<br>
 #define CSR_MCF  0x80<br>
 #define CSR_MAAS 0x40<br>
@@ -97,7 +98,7 @@ struct mpc_i2c {<br>
        u32 block;<br>
        int rc;<br>
        int expect_rxack;<br>
-<br>
+       bool has_errata_A004447;<br>
 };<br>
<br>
 struct mpc_i2c_divider {<br>
@@ -136,6 +137,83 @@ static void mpc_i2c_fixup(struct mpc_i2c *i2c)<br>
        }<br>
 }<br>
<br>
+static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)<br>
+{<br>
+       unsigned long timeout = jiffies + usecs_to_jiffies(100);<br>
+       int ret = 0;<br>
+<br>
+       while ((readb(i2c->base + MPC_I2C_SR) & mask) == 0) {<br>
+               if (time_after(jiffies, timeout)) {<br>
+                       ret = -ETIMEDOUT;<br>
+                       break;<br>
+               }<br>
+               cond_resched();<br>
+       }<br>
+<br>
+       return ret;<br>
+}</blockquote><div><br></div><div>readb_poll_timeout()</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+<br>
+/*<br>
+ * Workaround for Erratum A004447. From the P2040CE Rev Q<br>
+ *<br>
+ * 1.  Set up the frequency divider and sampling rate.<br>
+ * 2.  I2CCR - a0h<br>
+ * 3.  Poll for I2CSR[MBB] to get set.<br>
+ * 4.  If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to<br>
+ *     step 5. If MAL is not set, then go to step 13.<br>
+ * 5.  I2CCR - 00h<br>
+ * 6.  I2CCR - 22h<br>
+ * 7.  I2CCR - a2h<br>
+ * 8.  Poll for I2CSR[MBB] to get set.<br>
+ * 9.  Issue read to I2CDR.<br>
+ * 10. Poll for I2CSR[MIF] to be set.<br>
+ * 11. I2CCR - 82h<br>
+ * 12. Workaround complete. Skip the next steps.<br>
+ * 13. Issue read to I2CDR.<br>
+ * 14. Poll for I2CSR[MIF] to be set.<br>
+ * 15. I2CCR - 80h<br>
+ */<br>
+static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)<br>
+{<br>
+       int ret;<br>
+       u32 val;<br>
+<br>
+       writeccr(i2c, CCR_MEN | CCR_MSTA);<br>
+       ret = i2c_mpc_wait_sr(i2c, CSR_MBB);<br>
+       if (ret) {<br>
+               dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");<br>
+               return;<br>
+       }<br>
+<br>
+       val = readb(i2c->base + MPC_I2C_SR);<br>
+<br>
+       if (val & CSR_MAL) {<br>
+               writeccr(i2c, 0x00);<br>
+               writeccr(i2c, CCR_MSTA | CCR_RSVD);<br>
+               writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD);<br>
+               ret = i2c_mpc_wait_sr(i2c, CSR_MBB);<br>
+               if (ret) {<br>
+                       dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");<br>
+                       return;<br>
+               }<br>
+               val = readb(i2c->base + MPC_I2C_DR);<br>
+               ret = i2c_mpc_wait_sr(i2c, CSR_MIF);<br>
+               if (ret) {<br>
+                       dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");<br>
+                       return;<br>
+               }<br>
+               writeccr(i2c, CCR_MEN | CCR_RSVD);<br>
+       } else {<br>
+               val = readb(i2c->base + MPC_I2C_DR);<br>
+               ret = i2c_mpc_wait_sr(i2c, CSR_MIF);<br>
+               if (ret) {<br>
+                       dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");<br>
+                       return;<br>
+               }<br>
+               writeccr(i2c, CCR_MEN);<br>
+       }<br>
+}<br>
+<br>
 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)<br>
 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {<br>
        {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},<br>
@@ -670,7 +748,10 @@ static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)<br>
 {<br>
        struct mpc_i2c *i2c = i2c_get_adapdata(adap);<br>
<br>
-       mpc_i2c_fixup(i2c);<br>
+       if (i2c->has_errata_A004447)<br>
+               mpc_i2c_fixup_A004447(i2c);<br>
+       else<br>
+               mpc_i2c_fixup(i2c);<br>
<br>
        return 0;<br>
 }<br>
@@ -767,6 +848,9 @@ static int fsl_i2c_probe(struct platform_device *op)<br>
        }<br>
        dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);<br>
<br>
+       if (of_property_read_bool(op-><wbr>dev.of_node, "fsl,i2c-erratum-a004447"))<br>
+               i2c->has_errata_A004447 = true;<br>
+<br>
        i2c->adap = mpc_ops;<br>
        scnprintf(i2c-><a href="http://adap.name" target="_blank">adap.name</a>, sizeof(i2c-><a href="http://adap.name" target="_blank">adap.name</a>),<br>
                  "MPC adapter (%s)", of_node_full_name(op->dev.of_<wbr>node));<br>
-- <br>
2.31.1<br>
<br>
</blockquote><br><br>-- <br>With Best Regards,<br>Andy Shevchenko<br><br><br>