<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On 22-Jul-2020, at 9:48 AM, Jordan Niethe <<a href="mailto:jniethe5@gmail.com" class="">jniethe5@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><span style="caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none; float: none; display: inline !important;" class="">On Sat, Jul 18, 2020 at 1:02 AM Athira Rajeev</span><br style="caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none;" class=""><span style="caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none; float: none; display: inline !important;" class=""><</span><a href="mailto:atrajeev@linux.vnet.ibm.com" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px;" class="">atrajeev@linux.vnet.ibm.com</a><span style="caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none; float: none; display: inline !important;" class="">> wrote:</span><br style="caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none;" class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; text-decoration: none;" class=""><br class="">From: Madhavan Srinivasan <<a href="mailto:maddy@linux.ibm.com" class="">maddy@linux.ibm.com</a>><br class=""><br class="">PowerISA v3.1 includes new performance monitoring unit(PMU)<br class="">special purpose registers (SPRs). They are<br class=""><br class="">Monitor Mode Control Register 3 (MMCR3)<br class="">Sampled Instruction Event Register 2 (SIER2)<br class="">Sampled Instruction Event Register 3 (SIER3)<br class=""><br class="">MMCR3 is added for further sampling related configuration<br class="">control. SIER2/SIER3 are added to provide additional<br class="">information about the sampled instruction.<br class=""><br class="">Patch adds new PPMU flag called "PPMU_ARCH_310S" to support<br class="">handling of these new SPRs, updates the struct thread_struct<br class="">to include these new SPRs, include MMCR3 in struct mmcr_regs.<br class="">This is needed to support programming of MMCR3 SPR during<br class="">event_[enable/disable]. Patch also adds the sysfs support<br class="">for the MMCR3 SPR along with SPRN_ macros for these new pmu sprs.<br class=""><br class="">Signed-off-by: Madhavan Srinivasan <<a href="mailto:maddy@linux.ibm.com" class="">maddy@linux.ibm.com</a>><br class="">---<br class="">arch/powerpc/include/asm/perf_event_server.h | 2 ++<br class="">arch/powerpc/include/asm/processor.h | 4 ++++<br class="">arch/powerpc/include/asm/reg.h | 6 ++++++<br class="">arch/powerpc/kernel/sysfs.c | 8 ++++++++<br class="">arch/powerpc/perf/core-book3s.c | 29 ++++++++++++++++++++++++++++<br class="">5 files changed, 49 insertions(+)<br class=""><br class="">diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h<br class="">index 14b8dc1..832450a 100644<br class="">--- a/arch/powerpc/include/asm/perf_event_server.h<br class="">+++ b/arch/powerpc/include/asm/perf_event_server.h<br class="">@@ -22,6 +22,7 @@ struct mmcr_regs {<br class=""> unsigned long mmcr1;<br class=""> unsigned long mmcr2;<br class=""> unsigned long mmcra;<br class="">+ unsigned long mmcr3;<br class="">};<br class="">/*<br class=""> * This struct provides the constants and functions needed to<br class="">@@ -75,6 +76,7 @@ struct power_pmu {<br class="">#define PPMU_HAS_SIER 0x00000040 /* Has SIER */<br class="">#define PPMU_ARCH_207S 0x00000080 /* PMC is architecture v2.07S */<br class="">#define PPMU_NO_SIAR 0x00000100 /* Do not use SIAR */<br class="">+#define PPMU_ARCH_310S 0x00000200 /* Has MMCR3, SIER2 and SIER3 */<br class=""></blockquote><span style="caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none; float: none; display: inline !important;" class="">We elsewhere have CPU_FTR_ARCH_31, so should this be PPMU_ARCH_31S to</span><br style="caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none;" class=""><span style="caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none; float: none; display: inline !important;" class="">be consistent.</span><br style="caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none;" class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; text-decoration: none;" class=""><br class=""></blockquote></div></blockquote><div><br class=""></div>Ok,</div><div>This change will need to be done in all places which are currently using PPMU_ARCH_310S</div><div><br class=""><blockquote type="cite" class=""><div class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; text-decoration: none;" class="">/*<br class=""> * Values for flags to get_alternatives()<br class="">diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h<br class="">index 52a6783..a466e94 100644<br class="">--- a/arch/powerpc/include/asm/processor.h<br class="">+++ b/arch/powerpc/include/asm/processor.h<br class="">@@ -272,6 +272,10 @@ struct thread_struct {<br class=""> unsigned mmcr0;<br class=""><br class=""> unsigned used_ebb;<br class="">+ unsigned long mmcr3;<br class="">+ unsigned long sier2;<br class="">+ unsigned long sier3;<br class="">+<br class="">#endif<br class="">};<br class=""><br class="">diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h<br class="">index 88e6c78..21a1b2d 100644<br class="">--- a/arch/powerpc/include/asm/reg.h<br class="">+++ b/arch/powerpc/include/asm/reg.h<br class="">@@ -876,7 +876,9 @@<br class="">#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */<br class="">#define SPRN_MMCR1 798<br class="">#define SPRN_MMCR2 785<br class="">+#define SPRN_MMCR3 754<br class="">#define SPRN_UMMCR2 769<br class="">+#define SPRN_UMMCR3 738<br class="">#define SPRN_MMCRA 0x312<br class="">#define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */<br class="">#define MMCRA_SDAR_DCACHE_MISS 0x40000000UL<br class="">@@ -918,6 +920,10 @@<br class="">#define SIER_SIHV 0x1000000 /* Sampled MSR_HV */<br class="">#define SIER_SIAR_VALID 0x0400000 /* SIAR contents valid */<br class="">#define SIER_SDAR_VALID 0x0200000 /* SDAR contents valid */<br class="">+#define SPRN_SIER2 752<br class="">+#define SPRN_SIER3 753<br class="">+#define SPRN_USIER2 736<br class="">+#define SPRN_USIER3 737<br class="">#define SPRN_SIAR 796<br class="">#define SPRN_SDAR 797<br class="">#define SPRN_TACR 888<br class="">diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c<br class="">index 571b325..46b4ebc 100644<br class="">--- a/arch/powerpc/kernel/sysfs.c<br class="">+++ b/arch/powerpc/kernel/sysfs.c<br class="">@@ -622,8 +622,10 @@ void ppc_enable_pmcs(void)<br class="">SYSFS_PMCSETUP(pmc8, SPRN_PMC8);<br class=""><br class="">SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);<br class="">+SYSFS_PMCSETUP(mmcr3, SPRN_MMCR3);<br class=""><br class="">static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);<br class="">+static DEVICE_ATTR(mmcr3, 0600, show_mmcr3, store_mmcr3);<br class="">#endif /* HAS_PPC_PMC56 */<br class=""><br class=""><br class="">@@ -886,6 +888,9 @@ static int register_cpu_online(unsigned int cpu)<br class="">#ifdef CONFIG_PMU_SYSFS<br class=""> if (cpu_has_feature(CPU_FTR_MMCRA))<br class=""> device_create_file(s, &dev_attr_mmcra);<br class="">+<br class="">+ if (cpu_has_feature(CPU_FTR_ARCH_31))<br class="">+ device_create_file(s, &dev_attr_mmcr3);<br class="">#endif /* CONFIG_PMU_SYSFS */<br class=""><br class=""> if (cpu_has_feature(CPU_FTR_PURR)) {<br class="">@@ -980,6 +985,9 @@ static int unregister_cpu_online(unsigned int cpu)<br class="">#ifdef CONFIG_PMU_SYSFS<br class=""> if (cpu_has_feature(CPU_FTR_MMCRA))<br class=""> device_remove_file(s, &dev_attr_mmcra);<br class="">+<br class="">+ if (cpu_has_feature(CPU_FTR_ARCH_31))<br class="">+ device_remove_file(s, &dev_attr_mmcr3);<br class="">#endif /* CONFIG_PMU_SYSFS */<br class=""><br class=""> if (cpu_has_feature(CPU_FTR_PURR)) {<br class="">diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c<br class="">index f4d07b5..ca32fc0 100644<br class="">--- a/arch/powerpc/perf/core-book3s.c<br class="">+++ b/arch/powerpc/perf/core-book3s.c<br class="">@@ -72,6 +72,11 @@ struct cpu_hw_events {<br class="">/*<br class=""> * 32-bit doesn't have MMCRA but does have an MMCR2,<br class=""> * and a few other names are different.<br class="">+ * Also 32-bit doesn't have MMCR3, SIER2 and SIER3.<br class="">+ * Define them as zero knowing that any code path accessing<br class="">+ * these registers (via mtspr/mfspr) are done under ppmu flag<br class="">+ * check for PPMU_ARCH_310S and we will not enter that code path<br class="">+ * for 32-bit.<br class=""> */<br class="">#ifdef CONFIG_PPC32<br class=""><br class="">@@ -85,6 +90,9 @@ struct cpu_hw_events {<br class="">#define MMCR0_PMCC_U6 0<br class=""><br class="">#define SPRN_MMCRA SPRN_MMCR2<br class="">+#define SPRN_MMCR3 0<br class="">+#define SPRN_SIER2 0<br class="">+#define SPRN_SIER3 0<br class="">#define MMCRA_SAMPLE_ENABLE 0<br class=""><br class="">static inline unsigned long perf_ip_adjust(struct pt_regs *regs)<br class="">@@ -581,6 +589,11 @@ static void ebb_switch_out(unsigned long mmcr0)<br class=""> current->thread.sdar = mfspr(SPRN_SDAR);<br class=""> current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;<br class=""> current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;<br class="">+ if (ppmu->flags & PPMU_ARCH_310S) {<br class="">+ current->thread.mmcr3 = mfspr(SPRN_MMCR3);<br class=""></blockquote><span style="caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none; float: none; display: inline !important;" class="">Like MMCR0_USER_MASK and MMCR2_USER_MASK do we need a MMCR3_USER_MASK</span><br style="caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none;" class=""><span style="caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none; float: none; display: inline !important;" class="">here, or is there no need?</span><br style="caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none;" class=""></div></blockquote><div><br class=""></div>Jordan</div><div><br class=""></div><div>We don’t need user mask for MMCR3 and other new SPRs ( SIER2/3) . I<font face="Helvetica Neue" class="">ncase of MMCR3, we dont have any Freeze control bits and incase of SIER2/3, it is similar to SIER (where HW handles the masking of the bits), hence we didn't add any user_mask</font><span style="font-family: "Helvetica Neue";" class=""> </span><span style="font-family: "Helvetica Neue";" class="">for these SPRs</span></div><div><span style="font-family: "Helvetica Neue";" class=""><br class=""></span></div><div><span style="font-family: "Helvetica Neue";" class="">Thanks</span></div><div><span style="font-family: "Helvetica Neue";" class="">Athira</span></div><div><font face="Helvetica Neue" class=""><br class=""></font><blockquote type="cite" class=""><div class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; text-decoration: none;" class="">+ current->thread.sier2 = mfspr(SPRN_SIER2);<br class="">+ current->thread.sier3 = mfspr(SPRN_SIER3);<br class="">+ }<br class="">}<br class=""><br class="">static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)<br class="">@@ -620,6 +633,12 @@ static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)<br class=""> * instead manage the MMCR2 entirely by itself.<br class=""> */<br class=""> mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2 | current->thread.mmcr2);<br class="">+<br class="">+ if (ppmu->flags & PPMU_ARCH_310S) {<br class="">+ mtspr(SPRN_MMCR3, current->thread.mmcr3);<br class="">+ mtspr(SPRN_SIER2, current->thread.sier2);<br class="">+ mtspr(SPRN_SIER3, current->thread.sier3);<br class="">+ }<br class="">out:<br class=""> return mmcr0;<br class="">}<br class="">@@ -840,6 +859,11 @@ void perf_event_print_debug(void)<br class=""> pr_info("EBBRR: %016lx BESCR: %016lx\n",<br class=""> mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR));<br class=""> }<br class="">+<br class="">+ if (ppmu->flags & PPMU_ARCH_310S) {<br class="">+ pr_info("MMCR3: %016lx SIER2: %016lx SIER3: %016lx\n",<br class="">+ mfspr(SPRN_MMCR3), mfspr(SPRN_SIER2), mfspr(SPRN_SIER3));<br class="">+ }<br class="">#endif<br class=""> pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n",<br class=""> mfspr(SPRN_SIAR), sdar, sier);<br class="">@@ -1305,6 +1329,8 @@ static void power_pmu_enable(struct pmu *pmu)<br class=""> if (!cpuhw->n_added) {<br class=""> mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE);<br class=""> mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1);<br class="">+ if (ppmu->flags & PPMU_ARCH_310S)<br class="">+ mtspr(SPRN_MMCR3, cpuhw->mmcr.mmcr3);<br class=""> goto out_enable;<br class=""> }<br class=""><br class="">@@ -1348,6 +1374,9 @@ static void power_pmu_enable(struct pmu *pmu)<br class=""> if (ppmu->flags & PPMU_ARCH_207S)<br class=""> mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2);<br class=""><br class="">+ if (ppmu->flags & PPMU_ARCH_310S)<br class="">+ mtspr(SPRN_MMCR3, cpuhw->mmcr.mmcr3);<br class="">+<br class=""> /*<br class=""> * Read off any pre-existing events that need to move<br class=""> * to another PMC.<br class="">--<br class="">1.8.3.1</blockquote></div></blockquote></div><br class=""></body></html>