<html><body><p><tt><font size="2">"Linuxppc-dev" <linuxppc-dev-bounces+maddy=linux.vnet.ibm.com@lists.ozlabs.org> wrote on 27/05/2020 03:20:17 PM:<br><br>> From: "Athira Rajeev" <atrajeev@linux.vnet.ibm.com></font></tt><br><tt><font size="2">> To: linuxppc-dev@lists.ozlabs.org</font></tt><br><tt><font size="2">> Cc: ravi.bangoria@linux.ibm.com, atrajeev@linux.vnet.ibm.com, <br>> maddy@linux.vnet.ibm.com, linux-kernel@vger.kernel.org, <br>> acme@kernel.org, anju@linux.vnet.ibm.com, jolsa@kernel.org</font></tt><br><tt><font size="2">> Date: 28/05/2020 02:46 PM</font></tt><br><tt><font size="2">> Subject: [PATCH V4 1/2] powerpc/perf: Add support for outputting <br>> extended regs in perf intr_regs</font></tt><br><tt><font size="2">> Sent by: "Linuxppc-dev" <linuxppc-dev-bounces<br>> +maddy=linux.vnet.ibm.com@lists.ozlabs.org></font></tt><br><tt><font size="2">> <br>> From: Anju T Sudhakar <anju@linux.vnet.ibm.com><br>> <br>> Add support for perf extended register capability in powerpc.<br>> The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to indicate the<br>> PMU which support extended registers. The generic code define the mask<br>> of extended registers as 0 for non supported architectures.<br>> <br>> Patch adds extended regs support for power9 platform by<br>> exposing MMCR0, MMCR1 and MMCR2 registers.<br>> <br>> REG_RESERVED mask needs update to include extended regs.<br>> `PERF_REG_EXTENDED_MASK`, contains mask value of the supported registers,<br>> is defined at runtime in the kernel based on platform since the supported<br>> registers may differ from one processor version to another and hence the<br>> MASK value.<br>> <br>> with patch<br>> ----------<br>> <br>> available registers: r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11<br>> r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26<br>> r27 r28 r29 r30 r31 nip msr orig_r3 ctr link xer ccr softe<br>> trap dar dsisr sier mmcra mmcr0 mmcr1 mmcr2<br>> <br>> PERF_RECORD_SAMPLE(IP, 0x1): 4784/4784: 0 period: 1 addr: 0<br>> ... intr regs: mask 0xffffffffffff ABI 64-bit<br>> .... r0 0xc00000000012b77c<br>> .... r1 0xc000003fe5e03930<br>> .... r2 0xc000000001b0e000<br>> .... r3 0xc000003fdcddf800<br>> .... r4 0xc000003fc7880000<br>> .... r5 0x9c422724be<br>> .... r6 0xc000003fe5e03908<br>> .... r7 0xffffff63bddc8706<br>> .... r8 0x9e4<br>> .... r9 0x0<br>> .... r10 0x1<br>> .... r11 0x0<br>> .... r12 0xc0000000001299c0<br>> .... r13 0xc000003ffffc4800<br>> .... r14 0x0<br>> .... r15 0x7fffdd8b8b00<br>> .... r16 0x0<br>> .... r17 0x7fffdd8be6b8<br>> .... r18 0x7e7076607730<br>> .... r19 0x2f<br>> .... r20 0xc00000001fc26c68<br>> .... r21 0xc0002041e4227e00<br>> .... r22 0xc00000002018fb60<br>> .... r23 0x1<br>> .... r24 0xc000003ffec4d900<br>> .... r25 0x80000000<br>> .... r26 0x0<br>> .... r27 0x1<br>> .... r28 0x1<br>> .... r29 0xc000000001be1260<br>> .... r30 0x6008010<br>> .... r31 0xc000003ffebb7218<br>> .... nip 0xc00000000012b910<br>> .... msr 0x9000000000009033<br>> .... orig_r3 0xc00000000012b86c<br>> .... ctr 0xc0000000001299c0<br>> .... link 0xc00000000012b77c<br>> .... xer 0x0<br>> .... ccr 0x28002222<br>> .... softe 0x1<br>> .... trap 0xf00<br>> .... dar 0x0<br>> .... dsisr 0x80000000000<br>> .... sier 0x0<br>> .... mmcra 0x80000000000<br>> .... mmcr0 0x82008090<br>> .... mmcr1 0x1e000000<br>> .... mmcr2 0x0<br>> ... thread: perf:4784<br>> <br>> Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com><br>> [Defined PERF_REG_EXTENDED_MASK at run time to add support for <br>> different platforms ]<br>> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com><br>> Reviewed-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com></font></tt><br><br><tt><font size="2">Tested with 5.7.0-rc2</font></tt><br><tt><font size="2">Tested-by: Nageswara R Sastry <nasastry@in.ibm.com></font></tt><br><br><tt><font size="2"><br>> ---<br>> arch/powerpc/include/asm/perf_event_server.h | 8 +++++++<br>> arch/powerpc/include/uapi/asm/perf_regs.h | 14 +++++++++++-<br>> arch/powerpc/perf/core-book3s.c | 1 +<br>> arch/powerpc/perf/perf_regs.c | 34 +++++++++++++++++<br>> ++++++++---<br>> arch/powerpc/perf/power9-pmu.c | 6 +++++<br>> 5 files changed, 59 insertions(+), 4 deletions(-)<br>> <br>> diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/<br>> powerpc/include/asm/perf_event_server.h<br>> index 3e9703f..1458e1a 100644<br>> --- a/arch/powerpc/include/asm/perf_event_server.h<br>> +++ b/arch/powerpc/include/asm/perf_event_server.h<br>> @@ -15,6 +15,9 @@<br>> #define MAX_EVENT_ALTERNATIVES 8<br>> #define MAX_LIMITED_HWCOUNTERS 2<br>> <br>> +extern u64 mask_var;<br>> +#define PERF_REG_EXTENDED_MASK mask_var<br>> +<br>> struct perf_event;<br>> <br>> /*<br>> @@ -55,6 +58,11 @@ struct power_pmu {<br>> int *blacklist_ev;<br>> /* BHRB entries in the PMU */<br>> int bhrb_nr;<br>> + /*<br>> + * set this flag with `PERF_PMU_CAP_EXTENDED_REGS` if<br>> + * the pmu supports extended perf regs capability<br>> + */<br>> + int capabilities;<br>> };<br>> <br>> /*<br>> diff --git a/arch/powerpc/include/uapi/asm/perf_regs.h b/arch/<br>> powerpc/include/uapi/asm/perf_regs.h<br>> index f599064..485b1d5 100644<br>> --- a/arch/powerpc/include/uapi/asm/perf_regs.h<br>> +++ b/arch/powerpc/include/uapi/asm/perf_regs.h<br>> @@ -48,6 +48,18 @@ enum perf_event_powerpc_regs {<br>> PERF_REG_POWERPC_DSISR,<br>> PERF_REG_POWERPC_SIER,<br>> PERF_REG_POWERPC_MMCRA,<br>> - PERF_REG_POWERPC_MAX,<br>> + /* Extended registers */<br>> + PERF_REG_POWERPC_MMCR0,<br>> + PERF_REG_POWERPC_MMCR1,<br>> + PERF_REG_POWERPC_MMCR2,<br>> + /* Max regs without the extended regs */<br>> + PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1,<br>> };<br>> +<br>> +#define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1)<br>> +<br>> +/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 */<br>> +#define PERF_REG_PMU_MASK_300 (((1ULL << (PERF_REG_POWERPC_MMCR2 <br>> + 1)) - 1) \<br>> + - PERF_REG_PMU_MASK)<br>> +<br>> #endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */<br>> diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c<br>> index 3dcfecf..7f63edf 100644<br>> --- a/arch/powerpc/perf/core-book3s.c<br>> +++ b/arch/powerpc/perf/core-book3s.c<br>> @@ -2275,6 +2275,7 @@ int register_power_pmu(struct power_pmu *pmu)<br>> pmu->name);<br>> <br>> power_pmu.attr_groups = ppmu->attr_groups;<br>> + power_pmu.capabilities |= (ppmu->capabilities & <br>> PERF_PMU_CAP_EXTENDED_REGS);<br>> <br>> #ifdef MSR_HV<br>> /*<br>> diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c<br>> index a213a0a..c8a7e8c 100644<br>> --- a/arch/powerpc/perf/perf_regs.c<br>> +++ b/arch/powerpc/perf/perf_regs.c<br>> @@ -13,9 +13,11 @@<br>> #include <asm/ptrace.h><br>> #include <asm/perf_regs.h><br>> <br>> +u64 mask_var;<br>> +<br>> #define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r)<br>> <br>> -#define REG_RESERVED (~((1ULL << PERF_REG_POWERPC_MAX) - 1))<br>> +#define REG_RESERVED (~(PERF_REG_EXTENDED_MASK | PERF_REG_PMU_MASK))<br>> <br>> static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = {<br>> PT_REGS_OFFSET(PERF_REG_POWERPC_R0, gpr[0]),<br>> @@ -69,10 +71,26 @@<br>> PT_REGS_OFFSET(PERF_REG_POWERPC_MMCRA, dsisr),<br>> };<br>> <br>> +/* Function to return the extended register values */<br>> +static u64 get_ext_regs_value(int idx)<br>> +{<br>> + switch (idx) {<br>> + case PERF_REG_POWERPC_MMCR0:<br>> + return mfspr(SPRN_MMCR0);<br>> + case PERF_REG_POWERPC_MMCR1:<br>> + return mfspr(SPRN_MMCR1);<br>> + case PERF_REG_POWERPC_MMCR2:<br>> + return mfspr(SPRN_MMCR2);<br>> + default: return 0;<br>> + }<br>> +}<br>> +<br>> u64 perf_reg_value(struct pt_regs *regs, int idx)<br>> {<br>> - if (WARN_ON_ONCE(idx >= PERF_REG_POWERPC_MAX))<br>> - return 0;<br>> + u64 PERF_REG_EXTENDED_MAX;<br>> +<br>> + if (cpu_has_feature(CPU_FTR_ARCH_300))<br>> + PERF_REG_EXTENDED_MAX = PERF_REG_POWERPC_MMCR2 + 1;<br>> <br>> if (idx == PERF_REG_POWERPC_SIER &&<br>> (IS_ENABLED(CONFIG_FSL_EMB_PERF_EVENT) ||<br>> @@ -85,6 +103,16 @@ u64 perf_reg_value(struct pt_regs *regs, int idx)<br>> IS_ENABLED(CONFIG_PPC32)))<br>> return 0;<br>> <br>> + if (idx >= PERF_REG_POWERPC_MAX && idx < PERF_REG_EXTENDED_MAX)<br>> + return get_ext_regs_value(idx);<br>> +<br>> + /*<br>> + * If the idx is referring to value beyond the<br>> + * supported registers, return 0 with a warning<br>> + */<br>> + if (WARN_ON_ONCE(idx >= PERF_REG_EXTENDED_MAX))<br>> + return 0;<br>> +<br>> return regs_get_register(regs, pt_regs_offset[idx]);<br>> }<br>> <br>> diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c<br>> index 08c3ef7..4525090 100644<br>> --- a/arch/powerpc/perf/power9-pmu.c<br>> +++ b/arch/powerpc/perf/power9-pmu.c<br>> @@ -90,6 +90,8 @@ enum {<br>> #define POWER9_MMCRA_IFM3 0x00000000C0000000UL<br>> #define POWER9_MMCRA_BHRB_MASK 0x00000000C0000000UL<br>> <br>> +extern u64 mask_var;<br>> +<br>> /* Nasty Power9 specific hack */<br>> #define PVR_POWER9_CUMULUS 0x00002000<br>> <br>> @@ -434,6 +436,7 @@ static void power9_config_bhrb(u64 pmu_bhrb_filter)<br>> .cache_events = &power9_cache_events,<br>> .attr_groups = power9_pmu_attr_groups,<br>> .bhrb_nr = 32,<br>> + .capabilities = PERF_PMU_CAP_EXTENDED_REGS,<br>> };<br>> <br>> int init_power9_pmu(void)<br>> @@ -457,6 +460,9 @@ int init_power9_pmu(void)<br>> }<br>> }<br>> <br>> + /* Set the PERF_REG_EXTENDED_MASK here */<br>> + mask_var = PERF_REG_PMU_MASK_300;<br>> +<br>> rc = register_power_pmu(&power9_pmu);<br>> if (rc)<br>> return rc;<br>> -- <br>> 1.8.3.1<br>> <br></font></tt><BR>
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