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<div class="moz-cite-prefix">Hi Michael,<br>
On Tuesday 03 November 2015 02:46 PM, Michael Ellerman wrote:<br>
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<blockquote cite="mid:1446542195.23081.5.camel@ellerman.id.au"
type="cite">
<pre wrap="">On Tue, 2015-11-03 at 11:40 +0530, Anju T wrote:
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<pre wrap="">The perf infrastructure uses a bit mask to find out
valid registers to display. Define a register mask
for supported registers defined in asm/perf_regs.h.
The bit positions also correspond to register IDs
which is used by perf infrastructure to fetch the register
values.CONFIG_HAVE_PERF_REGS enables
sampling of the interrupted machine state.
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<pre wrap="">diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c
new file mode 100644
index 0000000..0520492
--- /dev/null
+++ b/arch/powerpc/perf/perf_regs.c
@@ -0,0 +1,92 @@
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/perf_event.h>
+#include <linux/bug.h>
+#include <linux/stddef.h>
+#include <asm/ptrace.h>
+#include <asm/perf_regs.h>
+
+#define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r)
+
+#define REG_RESERVED (~((1ULL << PERF_REG_POWERPC_MAX) - 1))
+
+static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = {
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR0, gpr[0]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR1, gpr[1]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR2, gpr[2]),
</pre>
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<snip>
I realise you're following the example of other architectures, but we have
almost this exact same structure in ptrace.c, see regoffset_table.
It would be really nice if we could share them between ptrace and perf.
cheers
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<br>
Thank you for reviewing the patch.<br>
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<p style="margin-bottom: 0cm; line-height: 100%">That is a great
suggestion.</p>
<p style="margin-bottom: 0cm; line-height: 100%">In ptrace.c the
structure doesn't include ORIG_R3. So,in that case what should we
do?</p>
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<blockquote cite="mid:1446542195.23081.5.camel@ellerman.id.au"
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Thanks and Regard <br>
Anju<br>
<br>
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