<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Wed, May 6, 2015 at 7:12 PM, Suman Tripathi <span dir="ltr"><<a href="mailto:stripathi@apm.com" target="_blank">stripathi@apm.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">This patch adds the arasan sdhci nodes to reuse the of-arasan<br>
driver for APM X-Gene SoC.<br>
<br>
Signed-off-by: Suman Tripathi <<a href="mailto:stripathi@apm.com">stripathi@apm.com</a>><br>
---<br>
 arch/arm64/boot/dts/apm/apm-mustang.dts |  4 +++<br>
 arch/arm64/boot/dts/apm/apm-storm.dtsi  | 43 +++++++++++++++++++++++++++++++++<br>
 2 files changed, 47 insertions(+)<br>
<br>
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts<br>
index 83578e7..7ccd517 100644<br>
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts<br>
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts<br>
@@ -52,3 +52,7 @@<br>
 &xgenet {<br>
        status = "ok";<br>
 };<br>
+<br>
+&sdhci0 {<br>
+       status = "ok";<br>
+};<br>
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi<br>
index c8d3e0e..b5d2698 100644<br>
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi<br>
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi<br>
@@ -145,6 +145,40 @@<br>
                                clock-output-names = "socplldiv2";<br>
                        };<br>
<br>
+                       ahbclk: ahbclk@1f2ac000 {<br>
+                               compatible = "apm,xgene-device-clock";<br>
+                               #clock-cells = <1>;<br>
+                               clocks = <&socplldiv2 0>;<br>
+                               reg = <0x0 0x1f2ac000 0x0 0x1000<br>
+                                       0x0 0x17000000 0x0 0x2000>;<br>
+                               reg-names = "csr-reg", "div-reg";<br>
+                               csr-offset = <0x0>;<br>
+                               csr-mask = <0x1>;<br>
+                               enable-offset = <0x8>;<br>
+                               enable-mask = <0x1>;<br>
+                               divider-offset = <0x164>;<br>
+                               divider-width = <0x5>;<br>
+                               divider-shift = <0x0>;<br>
+                               clock-output-names = "ahbclk";<br>
+                       };<br>
+<br>
+                       sdioclk: sdioclk@1f2ac000 {<br>
+                               compatible = "apm,xgene-device-clock";<br>
+                               #clock-cells = <1>;<br>
+                               clocks = <&socplldiv2 0>;<br>
+                               reg = <0x0 0x1f2ac000 0x0 0x1000<br>
+                                       0x0 0x17000000 0x0 0x2000>;<br>
+                               reg-names = "csr-reg", "div-reg";<br>
+                               csr-offset = <0x0>;<br>
+                               csr-mask = <0x2>;<br>
+                               enable-offset = <0x8>;<br>
+                               enable-mask = <0x2>;<br>
+                               divider-offset = <0x178>;<br>
+                               divider-width = <0x8>;<br>
+                               divider-shift = <0x0>;<br>
+                               clock-output-names = "sdioclk";<br>
+                       };<br>
+<br>
                        qmlclk: qmlclk {<br>
                                compatible = "apm,xgene-device-clock";<br>
                                #clock-cells = <1>;<br>
@@ -533,6 +567,15 @@<br>
                        interrupts = <0x0 0x4f 0x4>;<br>
                };<br>
<br>
+               sdhci0: sdhci@1c000000 {<br>
+                       compatible = "arasan,sdhci-4.9a";<br>
+                       reg = <0x0 0x1c000000 0x0 0x100>;<br>
+                       interrupts = <0x0 0x49 0x4>;<br>
+                       dma-coherent;<br>
+                       clock-names = "clk_xin", "clk_ahb";<br>
+                       clocks = <&sdioclk 0>, <&ahbclk 0>;<br>
+               };<br>
+<br>
                phy1: phy@1f21a000 {<br>
                        compatible = "apm,xgene-phy";<br>
                        reg = <0x0 0x1f21a000 0x0 0x100>;<br>
--<br>
1.8.2.1<br>
<br>
</blockquote></div><br>Any comments on this patch ??<br clear="all"><div><br></div>-- <br><div class="gmail_signature"><div dir="ltr"><div>Thanks,</div><div>with regards,</div>Suman Tripathi</div></div>
</div></div>