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<div class="moz-cite-prefix">On 01/06/2014 11:41 AM, Gavin Hu wrote:<br>
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cite="mid:CABiPGEcHxgmuLMcMN1ByutJC22RJPHSZf3n5gF9BgenbfQTJvA@mail.gmail.com"
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<div>Thanks your response. :) <br>
But that means that these optimitive operations like
atomic_add() aren't optimitive actully in PPC architecture,
right? Becuase they can be interrupted by loacl HW
interrupts. Theoretically, the ISR also can access the
atomic gloable variable.<br>
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Nope, my understand is that if you wanna sync kernel primitive code
with ISR, you have responsibility to disable local interrupts.
atomic_add does not guarantee to handle such case.<br>
<br>
Thanks<br>
Wei<br>
<br>
<blockquote
cite="mid:CABiPGEcHxgmuLMcMN1ByutJC22RJPHSZf3n5gF9BgenbfQTJvA@mail.gmail.com"
type="cite">
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<br>
<br>
The following codes are complete atomic_inc() copied from
arch/<br>
static __inline__ void atomic_add(int a, atomic_t *v)<br>
{<br>
int t;<br>
<br>
__asm__ __volatile__(<br>
"1: lwarx %0,0,%3 # atomic_add\n\<br>
add %0,%2,%0\n"<br>
PPC405_ERR77(0,%3)<br>
" stwcx. %0,0,%3 \n\<br>
bne- 1b"<br>
: "=&r" (t), "+m" (v->counter)<br>
: "r" (a), "r" (&v->counter)<br>
: "cc");<br>
}<br>
<br>
<br>
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BR<br>
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Gavin. Hu<br>
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<div class="gmail_extra"><br>
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<div class="gmail_quote">On Mon, Dec 30, 2013 at 9:54 AM, wyang
<span dir="ltr"><<a moz-do-not-send="true"
href="mailto:w90p710@gmail.com" target="_blank">w90p710@gmail.com</a>></span>
wrote:<br>
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<div>On 12/28/2013 01:41 PM, Gavin Hu wrote:<br>
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<div dir="ltr">Hi <br>
<div><br>
I notice that there is a pair ppc instructions
lwarx and stwcx used to atomtic operation for
instance, atomic_inc/atomic_dec.<br>
<br>
</div>
<div>In some ppc manuals, they more emphasize its
mechanism is that lwarx can reseve the target
memory address preventing other CORE from
modifying it.<br>
<br>
</div>
<div>I assume that there is atomtic operation
executing on the CORE0 in a multicore system. In
this situation, does the CORE0 disable the local
HW interrupt?<br>
</div>
<div>Can the executing process from the beginning of
lwarx and end of stwcx be interrupted by HW
interruptions/exceptions? Anyway, they are two
assembly instructions.<br>
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It should just like other arch, the processor should
response any interrupt after the execution of a
instruction, so the local HW interrupt is not disabled.<br>
<br>
Thanks<br>
Wei<br>
<blockquote type="cite">
<div class="im">
<div dir="ltr">
<div> <br>
Thanks a lot!<br>
</div>
<div><br>
"1: lwarx %0,0,%2 # atomic_inc\n\<br>
addic %0,%0,1\n"<br>
" stwcx. %0,0,%2 \n\<br>
<br>
<br>
</div>
<div>BR<br>
</div>
<div>Gavin. Hu<br>
</div>
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