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<div class="moz-cite-prefix">On 12/28/2013 01:41 PM, Gavin Hu wrote:<br>
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<div dir="ltr">Hi <br>
<div><br>
I notice that there is a pair ppc instructions lwarx and stwcx
used to atomtic operation for instance, atomic_inc/atomic_dec.<br>
<br>
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<div>In some ppc manuals, they more emphasize its mechanism is
that lwarx can reseve the target memory address preventing
other CORE from modifying it.<br>
<br>
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<div>I assume that there is atomtic operation executing on the
CORE0 in a multicore system. In this situation, does the CORE0
disable the local HW interrupt?<br>
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<div>Can the executing process from the beginning of lwarx and
end of stwcx be interrupted by HW interruptions/exceptions?
Anyway, they are two assembly instructions.<br>
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<br>
It should just like other arch, the processor should response any
interrupt after the execution of a instruction, so the local HW
interrupt is not disabled.<br>
<br>
Thanks<br>
Wei<br>
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<br>
Thanks a lot!<br>
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<div><br>
"1: lwarx %0,0,%2 # atomic_inc\n\<br>
addic %0,%0,1\n"<br>
" stwcx. %0,0,%2 \n\<br>
<br>
<br>
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<div>BR<br>
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<div>Gavin. Hu<br>
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