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<p class="MsoNormal">Hi<o:p></o:p></p>
<p class="MsoNormal">The P1020 manual states (in the PIC chapter) that in the “Internal Interrupt Destination” register, only 1 CPU (and not both) can be selected as the IRQ destination. How then can we achieve “interrupt spraying” for the PCI interrupt (we
want interrupts to be sent alternately to CPU0 and CPU1). Also, we changed the code to ignore the MPIC_SINGLE_DEST_CPU flag and set both CPUs in the destination of the PIC_IIDRn register. This does seem to work. But we’re not sure if we can rely on this behavior
and whether it will cause other problems.<o:p></o:p></p>
<p class="MsoNormal">Any advice appreciated<o:p></o:p></p>
<p class="MsoNormal">Thanks<o:p></o:p></p>
<p class="MsoNormal">-gopal<o:p></o:p></p>
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