<p><br>Hi Alex,</p>
<p>Thanks for your advice. We are trying to make a board-to-board connection without any additional hardware (eg. a switch). The boards use a 50-pin, right-angle MEC8-125-02-L-D-RA1 connector from SAMTEC and are connected trough a EEDP-016-12.00-RA1-RA2-2 cross cable from SAMTEC. I hope this information is sufficient since there is not much one can find about it on Google. In addition, you can see a picture of the board including the connector in the datasheet located at <a href="http://www.windriver.com/products/product-notes/SBC8548E-product-note.pdf">http://www.windriver.com/products/product-notes/SBC8548E-product-note.pdf</a>. It is the connector on the left side of the PCI-EX slot.</p>
<p>We have tried your suggestion but the situation does not change other than the lane-mode being set to single lane 0, it still locks up when trying to generate a maintenance transaction. I still think it is memory related since the lock up occurs when accessing the maintenance window. Although all memory related settings seems to be alright.</p>
<p>The kernel output is as follows:</p>
<p>Setting up RapidIO peer-to-peer network <a>/soc8548@e0000000/rapidio@c0000</a><br>fsl-of-rio e00c0000.rapidio: Of-device full name <a>/soc8548@e0000000/rapidio@c0000</a><br>fsl-of-rio e00c0000.rapidio: Regs: [mem 0xe00c0000-0xe00dffff]<br>
fsl-of-rio e00c0000.rapidio: LAW start 0x00000000c0000000, size 0x0000000010000000.<br>fsl-of-rio e00c0000.rapidio: pwirq: 48, bellirq: 50, txirq: 53, rxirq 54<br>fsl-of-rio e00c0000.rapidio: DeviceID is 0x0<br>fsl-of-rio e00c0000.rapidio: Configured as HOST<br>
fsl-of-rio e00c0000.rapidio: Overriding RIO_PORT setting to single lane 0<br>fsl-of-rio e00c0000.rapidio: RapidIO PHY type: serial<br>fsl-of-rio e00c0000.rapidio: Hardware port width: 4<br>fsl-of-rio e00c0000.rapidio: Training connection status: Single-lane 0<br>
fsl-of-rio e00c0000.rapidio: RapidIO Common Transport System size: 256<br>fsl-of-rio e00c0000.rapidio: LAW start 0x00000000c0000000, RIO Maintainance Window Size 0x400000,New Main Start: 0xd1080000<br>RIO: enumerate master port 0, RIO0 mport<br>
fsl_rio_config_read: index 0 destid 255 hopcount 0 offset 00000068 len 4<br>fsl_rio_config_read: Passed IS_ALIGNED.<br>fsl_rio_config_read: Passed 'out_be32_1'<br>fsl_rio_config_read: Passed 'out_be32_2'<br>
fsl_rio_config_read: len is 4<br>fsl_rio_config_read: triggering '__fsl_read_rio_config'<br>fsl_rio_config_read: going to request to read data at d108006</p>
<p>Regards,<br>Bastiaan</p>
<div class="gmail_quote">2010/10/4 Bounine, Alexandre <span dir="ltr"><<a href="mailto:Alexandre.Bounine@idt.com">Alexandre.Bounine@idt.com</a>></span><br>
<blockquote class="gmail_quote" style="PADDING-LEFT: 1ex; MARGIN: 0px 0px 0px 0.8ex; BORDER-LEFT: #ccc 1px solid">Hi Bastiaan,<br><br>Are you trying board-to-board connection?<br>I am not familiar with WRS SBC8548 board - which type of connector they<br>
use for SRIO?<br><br>Assuming that all configuration is correct,<br>I would recommend first to try setting up x1 link mode at the lowest<br>link speed.<br>The x4 mode may present challenges in some cases.<br><br>For quick test you may just add port width override into fsl_rio.c<br>
like shown below (ugly but sometimes it helps ;) ):<br><br>@@ -1461,10 +1461,16 @@ int fsl_rio_setup(struct platform_device *dev)<br> rio_register_mport(port);<br><br> priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1);<br>
rio_regs_win = priv->regs_win;<br><br>+dev_info(&dev->dev, "Overriding RIO_PORT setting to single lane 0\n");<br>+out_be32(priv->regs_win + 0x15C, in_be32(priv->regs_win + 0x15C) |<br>0x800000);<br>
+out_be32(priv->regs_win + 0x15C, in_be32(priv->regs_win + 0x15C) |<br>0x2000000);<br>+out_be32(priv->regs_win + 0x15C, in_be32(priv->regs_win + 0x15C) &<br>~0x800000);<br>+msleep(100);<br>+<br> /* Probe the master port phy type */<br>
ccsr = in_be32(priv->regs_win + RIO_CCSR);<br> port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;<br> dev_info(&dev->dev, "RapidIO PHY type: %s\n",<br> (port->phy_type == RIO_PHY_PARALLEL) ?<br>
"parallel" :<br><br><br>Let me know what happens.<br>Please keep me in the CC: list next time when posting RapidIO questions<br>to the linuxppc-dev or kernel mailing lists.<br><br>Regards,<br><br>Alex.<br><br></blockquote>
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