Index: linux/arch/powerpc/kernel/cpu_setup_fsl_booke.S
===================================================================
--- linux/arch/powerpc/kernel/cpu_setup_fsl_booke.S	(revision 2871)
+++ linux/arch/powerpc/kernel/cpu_setup_fsl_booke.S	(working copy)
@@ -57,8 +57,14 @@
 	ori	r3,r3,HID0_DAPUEN@l
 	mtspr	SPRN_HID0,r3
 	b	__setup_e200_ivors
+_GLOBAL(__setup_cpu_e500v2)
+#ifdef CONFIG_PTE_64BIT
+	/* enable mas7 register for tlbre/tlbsx */
+	mfspr	r2,SPRN_HID0
+	ori 	r2,r2,HID0_EN_MAS7_UPDATE@l
+	mtspr	SPRN_HID0,r2
+#endif
 _GLOBAL(__setup_cpu_e500v1)
-_GLOBAL(__setup_cpu_e500v2)
 	mflr	r4
 	bl	__e500_icache_setup
 	bl	__e500_dcache_setup
Index: linux/arch/powerpc/include/asm/reg.h
===================================================================
--- linux/arch/powerpc/include/asm/reg.h	(revision 2871)
+++ linux/arch/powerpc/include/asm/reg.h	(working copy)
@@ -276,6 +276,7 @@
 #define HID0_DAPUEN	(1<<8)		/* Debug APU enable */
 #define HID0_SGE	(1<<7)		/* Store Gathering Enable */
 #define HID0_SIED	(1<<7)		/* Serial Instr. Execution [Disable] */
+#define HID0_EN_MAS7_UPDATE (1<<7)	/* Enable MAS7 reg for tlbre/tlbsx */
 #define HID0_DCFA	(1<<6)		/* Data Cache Flush Assist */
 #define HID0_LRSTK	(1<<4)		/* Link register stack - 745x */
 #define HID0_BTIC	(1<<5)		/* Branch Target Instr Cache Enable */