<table cellspacing="0" cellpadding="0" border="0" ><tr><td valign="top" style="font: inherit;">Hi,<br>I am trying to set a page of my data-structure as read-only on a USI MPC8347E.<br>This is primarily to figure a data structure corruption issue.<br>Added small support as follows:<br>ppc/mm/init.c:MMU_setup<br><br> __map_without_bats = 1;<br> __map_without_ltlbs = 1;<br><br><br>ppc/mm/pgtable.c<br><br>static int __change_page_attr(struct page *page, pgprot_t prot)<br>{<br> pte_t *kpte;<br> pmd_t *kpmd;<br> unsigned long address;<br><br> BUG_ON(PageHighMem(page));<br> address = (unsigned long)page_address(page);<br><br> if (v_mapped_by_bats(address) || v_mapped_by_tlbcam(address))<br> return 0;<br> if (!get_pteptr(&init_mm, address, &kpte,
&kpmd))<br> return -EINVAL;<br> set_pte_at(&init_mm, address, kpte, mk_pte(page, prot));<br> wmb();<br> flush_HPTE(0, address, pmd_val(*kpmd));<br> pte_unmap(kpte);<br> mb();<br> return 0;<br>}<br><br>/*<br> * Change the page attributes of an page in the linear mapping.<br>*/<br>int change_page_attr(struct page *page, int numpages, pgprot_t prot)<br>{<br> int i, err = 0;<br> unsigned long flags;<br><br> local_irq_save(flags);<br> for (i = 0; i < numpages; i++, page++) {<br> err = __change_page_attr(page, prot);<br> if (err)<br> break;<br>
}<br> local_irq_restore(flags);<br> return err;<br>}<br>EXPORT_SYMBOL(change_page_attr);<br><br>After allocation of my data structure, when I mark the page readonly like this:<br>change_page_attr(virt_to_page(dat_str), 1, PAGE_READONLY);<br><br>it works (throws Oops) but only for the first time, but subsequent writes<br>are going through. I expect even the subsequent writes to fail.<br><br>One more quirkiness to this is, after changing the page attribute I need to<br>read the element at least once for this to work.<br><br>Have I written the supportive api's (above ) correctly ? This is on 2.6.18 kernel.<br>If there is any other way to catch this corruption please let me know.<br>kgdb and bdi won't help me as it is a dynamically created data-structure and I<br>have timing constraints.<br><br>Regards,<br>Maindoor.<br><br></td></tr></table><br>