<br><br><div class="gmail_quote">On Thu, Apr 9, 2009 at 2:46 PM, Josh Boyer <span dir="ltr"><<a href="mailto:jwboyer@linux.vnet.ibm.com">jwboyer@linux.vnet.ibm.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
<div><div></div><div class="h5">On Wed, Apr 08, 2009 at 03:11:25PM -0600, John Linn wrote:<br>
>From: Suneel <[mailto:<a href="mailto:suneel.garapati@xilinx.com">suneel.garapati@xilinx.com</a>]><br>
><br>
>Added support for the new xps tft controller.<br>
><br>
>The new core has PLB interface support in addition to existing<br>
>DCR interface.<br>
><br>
>The driver has been modified to support this new core which<br>
>can be connected on PLB or DCR bus.<br>
><br>
>Signed-off-by: Suneel <<a href="mailto:suneelg@xilinx.com">suneelg@xilinx.com</a>><br>
>Signed-off-by: John Linn <<a href="mailto:john.linn@xilinx.com">john.linn@xilinx.com</a>><br>
>---<br>
> drivers/video/xilinxfb.c | 227 ++++++++++++++++++++++++++++++++--------------<br>
> 1 files changed, 160 insertions(+), 67 deletions(-)<br>
><br>
>diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c<br>
>index a82c530..a28a834 100644<br>
>--- a/drivers/video/xilinxfb.c<br>
>+++ b/drivers/video/xilinxfb.c<br>
>@@ -1,17 +1,24 @@<br>
> /*<br>
>- * xilinxfb.c<br>
> *<br>
>- * Xilinx TFT LCD frame buffer driver<br>
>+ * Xilinx TFT frame buffer driver<br>
> *<br>
> * Author: MontaVista Software, Inc.<br>
> * <a href="mailto:source@mvista.com">source@mvista.com</a><br>
> *<br>
> * 2002-2007 (c) MontaVista Software, Inc.<br>
> * 2007 (c) Secret Lab Technologies, Ltd.<br>
>+ * 2009 (c) Xilinx Inc.<br>
> *<br>
>- * This file is licensed under the terms of the GNU General Public License<br>
>- * version 2. This program is licensed "as is" without any warranty of any<br>
>- * kind, whether express or implied.<br>
>+ * This program is free software; you can redistribute it<br>
>+ * and/or modify it under the terms of the GNU General Public<br>
>+ * License as published by the Free Software Foundation;<br>
>+ * either version 2 of the License, or (at your option) any<br>
>+ * later version.<br>
>+ *<br>
>+ * You should have received a copy of the GNU General Public<br>
>+ * License along with this program; if not, write to the Free<br>
>+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA<br>
>+ * 02139, USA.<br>
> */<br>
<br>
</div></div>What Stephen said.<br>
<div class="im"><br>
> #define NUM_REGS 2<br>
> #define REG_FB_ADDR 0<br>
>@@ -112,6 +123,11 @@ struct xilinxfb_drvdata {<br>
><br>
> struct fb_info info; /* FB driver info record */<br>
><br>
>+ u32 regs_phys; /* phys. address of the control<br>
>+ registers */<br>
<br>
</div>Is this driver usable on the 440 based Xilinx devices? If so, is it possible<br>
to have the physical address of the registers above 4GiB, so is common with<br>
almost all the I/O on the other 440 boards?<br>
<div class="im"><br></div></blockquote></div><br>The driver works fine on 440 based Xilinx boards (the ML510 I use has a 440 core). It might be nice to move physical addresses above 4GB for devices but in all Xilinx tools and reference designs addresses below 4GB are used for periperhals and I think even below 2GB (or even below 1GB). It depends on the design.<br>
<br>Roderick Colenbrander<br>