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<DIV dir=ltr align=left><SPAN class=310524805-06032009><FONT face=Arial
color=#0000ff size=2>could you try to set '1' to DMA description
bit3?</FONT></SPAN></DIV><BR>
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<FONT face=Tahoma size=2><B>From:</B> Liu Dave-R63238 <BR><B>Sent:</B> Friday,
March 06, 2009 1:41 PM<BR><B>To:</B> 'Ben Menchaca'<BR><B>Cc:</B>
linuxppc-dev@ozlabs.org<BR><B>Subject:</B> RE: 83xx: Marking or Allocating
Pages as Cache-Inhibited<BR></FONT><BR></DIV>
<DIV></DIV>
<DIV dir=ltr align=left><SPAN class=249334005-06032009><FONT face=Arial
color=#0000ff size=2>what is the value of ACR
register?</FONT></SPAN></DIV><BR>
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<FONT face=Tahoma size=2><B>From:</B> Ben Menchaca
[mailto:ben.menchaca@gmail.com] <BR><B>Sent:</B> Friday, March 06, 2009 1:38
PM<BR><B>To:</B> Liu Dave-R63238<BR><B>Cc:</B>
linuxppc-dev@ozlabs.org<BR><B>Subject:</B> Re: 83xx: Marking or Allocating
Pages as Cache-Inhibited<BR></FONT><BR></DIV>
<DIV></DIV><FONT style="FONT-SIZE: 10pt; FONT-FAMILY: Tahoma"><FONT
style="FONT-SIZE: 10pt; FONT-FAMILY: Tahoma"><FONT
style="FONT-SIZE: 10pt; FONT-FAMILY: Tahoma"><FONT
style="FONT-SIZE: 10pt; FONT-FAMILY: Tahoma"><FONT
style="FONT-SIZE: 10pt; FONT-FAMILY: Tahoma">1. BAT2 in linux is set
to WIMG=0010, and covers all 64M<BR>2. PEX_DEVICE_CONTROL in PCI-E
Config Space (0x54): 0x1020<BR>3. PEX_xDMA_CTRL is set to
<SPAN></SPAN>0x00000401 at the initiation of the DMA.<BR>4. OWAR0 is
set to 0xFFFFF005, so NSNP is 0.<BR>5. The DMA descriptor (randomly
chosen when I hit a trigger...just ignore the size...) contains 0002AFF3 at
offset 0, so nosnoops are cleared.</FONT></FONT></FONT></FONT></FONT><FONT
style="FONT-SIZE: 10pt; FONT-FAMILY: Tahoma"><FONT
style="FONT-SIZE: 10pt; FONT-FAMILY: Tahoma"><FONT
style="FONT-SIZE: 10pt; FONT-FAMILY: Tahoma"><FONT
style="FONT-SIZE: 10pt; FONT-FAMILY: Tahoma"> <BR><BR>Core is 400MHz,
and CSB is 133MHz.</FONT></FONT></FONT></FONT><BR><FONT color=#888888><BR>-
Ben<BR></FONT><BR>
<DIV class=gmail_quote>On Thu, Mar 5, 2009 at 11:27 PM, Liu Dave-R63238
<SPAN dir=ltr><<A
href="mailto:DaveLiu@freescale.com">DaveLiu@freescale.com</A>></SPAN>
wrote:<BR>
<BLOCKQUOTE class=gmail_quote
style="PADDING-LEFT: 1ex; MARGIN: 0pt 0pt 0pt 0.8ex; BORDER-LEFT: rgb(204,204,204) 1px solid">and
what settings is DMA description bit 3?<BR>
<DIV class=im><BR>> -----Original Message-----<BR>> From:
linuxppc-dev-bounces+daveliu=<A href="http://freescale.com"
target=_blank>freescale.com</A>@<A href="http://ozlabs.org"
target=_blank>ozlabs.org</A><BR>> [mailto:<A
href="mailto:linuxppc-dev-bounces%2Bdaveliu">linuxppc-dev-bounces+daveliu</A>=<A
href="http://freescale.com" target=_blank>freescale.com</A>@<A
href="http://ozlabs.org" target=_blank>ozlabs.org</A>]<BR></DIV>
<DIV>
<DIV></DIV>
<DIV class=h5>> On Behalf Of Liu Dave-R63238<BR>> Sent:
Friday, March 06, 2009 1:22 PM<BR>> To: Ben Menchaca; <A
href="mailto:linuxppc-dev@ozlabs.org">linuxppc-dev@ozlabs.org</A><BR>>
Subject: RE: 83xx: Marking or Allocating Pages as
Cache-Inhibited<BR>><BR>> Did you enable the snoop bit at
PEX_WDMA_CTRL[SNOOP] and<BR>> PEX_RDMA_CTRL[SNOOP]?<BR>><BR>>
What is the freq settings? CORE/CSB bus.<BR>><BR>> Thanks,
Dave<BR>><BR>> ________________________________<BR>><BR>>
From: linuxppc-dev-bounces+daveliu=<A
href="http://freescale.com" target=_blank>freescale.com</A>@<A
href="http://ozlabs.org" target=_blank>ozlabs.org</A><BR>> [mailto:<A
href="mailto:linuxppc-dev-bounces%2Bdaveliu">linuxppc-dev-bounces+daveliu</A>=<A
href="http://freescale.com" target=_blank>freescale.com</A>@<A
href="http://ozlabs.org" target=_blank>ozlabs.org</A>]<BR>> On
Behalf Of Ben Menchaca<BR>> Sent: Friday, March
06, 2009 12:33 PM<BR>> To: <A
href="mailto:linuxppc-dev@ozlabs.org">linuxppc-dev@ozlabs.org</A><BR>>
Subject: 83xx: Marking or Allocating Pages as
Cache-Inhibited<BR>><BR>><BR>> I am working
on a Freescale 8314e design, and the<BR>> embedded device is configured
as a PCI-e endpoint running a<BR>> 2.6.27-5 kernel. For context,
we have written a kernel<BR>> module which, among other things, uses
the RDMA/WDMA engine<BR>> in the PCI-e IP block. On the host
side, these DMAs are<BR>> coherent. However, on the embedded
side, things are quite a<BR>> bit less rosy; we must manually
flush/invalidate cache lines<BR>> for WDMA/RDMAs to occur successfully.
After speaking with<BR>> (several) FAEs at Freescale, we believe
there is a<BR>> configuration issue that is the cause, but we have yet
to<BR>> have anyone successfully point to it.<BR>><BR>>
Disabling the data cache altogether resolves the
issue<BR>> entirely, but of course, also completely tanks
performance.<BR>> As a temporary workaround, I would like to simply
mark the<BR>> pages (obtained currently via dma_alloc_coherent)
involved as<BR>> cache-inhibited. I have attempted to do this via
some<BR>> snippets remaining in fec.c (va_to_pte, uncache_pte to
set<BR>> _PAGE_NO_CACHE, flush_tlb_page, then unmap_pte), but this
is<BR>> almost certainly braindead; va_to_pte is not a part of
the<BR>> 83xx source, as far as I can tell; 8xx only.<BR>><BR>>
A quick pointer in the correct direction for
marking<BR>> pages as cache-inhibited on a 2.6.27-5 kernel would
be<BR>> appreciated, or if my approach to a workaround is flawed,
a<BR>> pointer to the correct way would be great.<BR>><BR>>
Ben Menchaca<BR>><BR>><BR></DIV></DIV>>
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