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<DIV><FONT face=Verdana color=#000080 size=2></FONT> </DIV>
<DIV><FONT face=Verdana color=#c0c0c0 size=2>2008-09-18 </FONT></DIV><FONT
face=Verdana color=#000080 size=2>
<HR style="WIDTH: 122px; HEIGHT: 2px" align=left SIZE=2>
</FONT>
<DIV><FONT face=Verdana color=#c0c0c0 size=2><SPAN>limitjiang</SPAN>
</FONT></DIV><FONT face=Verdana color=#000080 size=2>
<HR>
</FONT>
<DIV><FONT face=Verdana size=2><STRONG>发件人：</STRONG>
linuxppc-dev-request@ozlabs.org </FONT></DIV>
<DIV><FONT face=Verdana size=2><STRONG>发送时间：</STRONG> 2008-09-18 09:55:11
</FONT></DIV>
<DIV><FONT face=Verdana size=2><STRONG>收件人：</STRONG> linuxppc-dev@ozlabs.org
</FONT></DIV>
<DIV><FONT face=Verdana size=2><STRONG>抄送：</STRONG> </FONT></DIV>
<DIV><FONT face=Verdana size=2><STRONG>主题：</STRONG> Linuxppc-dev Digest, Vol 49,
Issue 89 </FONT></DIV>
<DIV><FONT face=Verdana size=2></FONT> </DIV>
<DIV><FONT face=Verdana size=2>
<DIV>Send Linuxppc-dev mailing list submissions to</DIV>
<DIV>linuxppc-dev@ozlabs.org</DIV>
<DIV> </DIV>
<DIV>To subscribe or unsubscribe via the World Wide Web, visit</DIV>
<DIV>https://ozlabs.org/mailman/listinfo/linuxppc-dev</DIV>
<DIV>or, via email, send a message with subject or body 'help' to</DIV>
<DIV>linuxppc-dev-request@ozlabs.org</DIV>
<DIV> </DIV>
<DIV>You can reach the person managing the list at</DIV>
<DIV>linuxppc-dev-owner@ozlabs.org</DIV>
<DIV> </DIV>
<DIV>When replying, please edit your Subject line so it is more specific</DIV>
<DIV>than "Re: Contents of Linuxppc-dev digest..."</DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>Today's Topics:</DIV>
<DIV> </DIV>
<DIV> 1. [PATCH v7 2/4] powerpc: Fixes for CONFIG_PTE_64BIT for SMP</DIV>
<DIV> support (Kumar Gala)</DIV>
<DIV> 2. [PATCH v7 3/4] powerpc/fsl-booke: Fixup 64-bit PTE reading</DIV>
<DIV> for SMP
support (Kumar Gala)</DIV>
<DIV> 3. [PATCH v7 4/4] powerpc/mm: Implement _PAGE_SPECIAL &</DIV>
<DIV> pte_special()
for 32-bit (Kumar Gala)</DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>----------------------------------------------------------------------</DIV>
<DIV> </DIV>
<DIV>Message: 1</DIV>
<DIV>Date: Wed, 17 Sep 2008 18:00:03 -0500</DIV>
<DIV>From: Kumar Gala <galak@kernel.crashing.org ></DIV>
<DIV>Subject: [PATCH v7 2/4] powerpc: Fixes for CONFIG_PTE_64BIT for SMP</DIV>
<DIV>support</DIV>
<DIV>To: linuxppc-dev@ozlabs.org</DIV>
<DIV>Message-ID:</DIV>
<DIV><1221692405-19880-2-git-send-email-galak@kernel.crashing.org ></DIV>
<DIV> </DIV>
<DIV>There are some minor issues with support 64-bit PTEs on a 32-bit processor</DIV>
<DIV>when dealing with SMP.</DIV>
<DIV> </DIV>
<DIV>* We need to order the stores in set_pte_at to make sure the flag word</DIV>
<DIV> is set second.</DIV>
<DIV>* Change pte_clear to use pte_update so only the flag word is cleared</DIV>
<DIV>* Added a check to set_pte_at to clear the pte if it happened to be set.</DIV>
<DIV> </DIV>
<DIV>Signed-off-by: Kumar Gala <galak@kernel.crashing.org
></DIV>
<DIV>---</DIV>
<DIV> </DIV>
<DIV>Changed the set_pte_at checking to deal with the case that it's called</DIV>
<DIV>with a pte that has pte_present and clearing it w/proper ordering.</DIV>
<DIV> </DIV>
<DIV>- k</DIV>
<DIV> </DIV>
<DIV> arch/powerpc/include/asm/highmem.h | 2 +-</DIV>
<DIV> arch/powerpc/include/asm/pgtable-ppc32.h | 28 +++++++++++++++++++++++-----</DIV>
<DIV> 2 files changed, 24 insertions(+), 6 deletions(-)</DIV>
<DIV> </DIV>
<DIV>diff --git a/arch/powerpc/include/asm/highmem.h b/arch/powerpc/include/asm/highmem.h</DIV>
<DIV>index 5d99b64..91c5895 100644</DIV>
<DIV>--- a/arch/powerpc/include/asm/highmem.h</DIV>
<DIV>+++ b/arch/powerpc/include/asm/highmem.h</DIV>
<DIV>@@ -84,7 +84,7 @@ static inline void *kmap_atomic_prot(struct page *page, enum km_type type, pgpro</DIV>
<DIV> #ifdef CONFIG_DEBUG_HIGHMEM</DIV>
<DIV> BUG_ON(!pte_none(*(kmap_pte-idx)));</DIV>
<DIV> #endif</DIV>
<DIV>-
set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));</DIV>
<DIV>+
__set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));</DIV>
<DIV> flush_tlb_page(NULL, vaddr);</DIV>
<DIV> </DIV>
<DIV> return (void*) vaddr;</DIV>
<DIV>diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h</DIV>
<DIV>index 6fe39e3..d1d23b9 100644</DIV>
<DIV>--- a/arch/powerpc/include/asm/pgtable-ppc32.h</DIV>
<DIV>+++ b/arch/powerpc/include/asm/pgtable-ppc32.h</DIV>
<DIV>@@ -517,7 +517,8 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);</DIV>
<DIV> </DIV>
<DIV> #define pte_none(pte)
((pte_val(pte) & ~_PTE_NONE_MASK) == 0)</DIV>
<DIV> #define pte_present(pte)
(pte_val(pte) & _PAGE_PRESENT)</DIV>
<DIV>-#define pte_clear(mm,addr,ptep)
do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)</DIV>
<DIV>+#define pte_clear(mm, addr, ptep) \</DIV>
<DIV>+
do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)</DIV>
<DIV> </DIV>
<DIV> #define pmd_none(pmd) (!pmd_val(pmd))</DIV>
<DIV> #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)</DIV>
<DIV>@@ -612,9 +613,6 @@ static inline unsigned long pte_update(pte_t *p,</DIV>
<DIV> return old;</DIV>
<DIV> }</DIV>
<DIV> #else /* CONFIG_PTE_64BIT */</DIV>
<DIV>-/* TODO: Change that to only modify the low word and move set_pte_at()</DIV>
<DIV>- * out of line</DIV>
<DIV>- */</DIV>
<DIV> static inline unsigned long long pte_update(pte_t *p,</DIV>
<DIV> unsigned long clr,</DIV>
<DIV> unsigned long set)</DIV>
<DIV>@@ -652,16 +650,36 @@ static inline unsigned long long pte_update(pte_t *p,</DIV>
<DIV> * On machines which use an MMU hash table we avoid changing the</DIV>
<DIV> * _PAGE_HASHPTE bit.</DIV>
<DIV> */</DIV>
<DIV>-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,</DIV>
<DIV>+</DIV>
<DIV>+static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,</DIV>
<DIV>
pte_t *ptep, pte_t pte)</DIV>
<DIV> {</DIV>
<DIV> #if _PAGE_HASHPTE != 0</DIV>
<DIV>
pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);</DIV>
<DIV>+#elif defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP)</DIV>
<DIV>+ __asm__ __volatile__("\</DIV>
<DIV>+ stw%U0%X0 %2,%0\n\</DIV>
<DIV>+ eieio\n\</DIV>
<DIV>+ stw%U0%X0 %L2,%1"</DIV>
<DIV>+
: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))</DIV>
<DIV>+ : "r" (pte) : "memory");</DIV>
<DIV> #else</DIV>
<DIV> *ptep = pte;</DIV>
<DIV> #endif</DIV>
<DIV> }</DIV>
<DIV> </DIV>
<DIV>+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,</DIV>
<DIV>+
pte_t *ptep, pte_t pte)</DIV>
<DIV>+{</DIV>
<DIV>+#if defined(CONFIG_PTE_64BIT)</DIV>
<DIV>+ if (unlikely(pte_present(*ptep))) {</DIV>
<DIV>+ pte_clear(mm, addr, ptep);</DIV>
<DIV>+ smp_wmb();</DIV>
<DIV>+ }</DIV>
<DIV>+#endif</DIV>
<DIV>+ __set_pte_at(mm, addr, ptep, pte);</DIV>
<DIV>+}</DIV>
<DIV>+</DIV>
<DIV> /*</DIV>
<DIV> * 2.6 calls this without flushing the TLB entry; this is wrong</DIV>
<DIV> * for our hash-based implementation, we fix that up here.</DIV>
<DIV>-- </DIV>
<DIV>1.5.5.1</DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>------------------------------</DIV>
<DIV> </DIV>
<DIV>Message: 2</DIV>
<DIV>Date: Wed, 17 Sep 2008 18:00:04 -0500</DIV>
<DIV>From: Kumar Gala <galak@kernel.crashing.org ></DIV>
<DIV>Subject: [PATCH v7 3/4] powerpc/fsl-booke: Fixup 64-bit PTE reading</DIV>
<DIV>for SMP support</DIV>
<DIV>To: linuxppc-dev@ozlabs.org</DIV>
<DIV>Message-ID:</DIV>
<DIV><1221692405-19880-3-git-send-email-galak@kernel.crashing.org ></DIV>
<DIV> </DIV>
<DIV>We need to create a false data dependency to ensure the loads of</DIV>
<DIV>the pte are done in the right order.</DIV>
<DIV> </DIV>
<DIV>Signed-off-by: Kumar Gala <galak@kernel.crashing.org
></DIV>
<DIV>---</DIV>
<DIV> arch/powerpc/kernel/head_fsl_booke.S | 26 +++++++++++++++++++++-----</DIV>
<DIV> 1 files changed, 21 insertions(+), 5 deletions(-)</DIV>
<DIV> </DIV>
<DIV>diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S</DIV>
<DIV>index 3cb52fa..377e0c1 100644</DIV>
<DIV>--- a/arch/powerpc/kernel/head_fsl_booke.S</DIV>
<DIV>+++ b/arch/powerpc/kernel/head_fsl_booke.S</DIV>
<DIV>@@ -579,13 +579,19 @@ interrupt_base:</DIV>
<DIV> </DIV>
<DIV> FIND_PTE</DIV>
<DIV> andc. r13,r13,r11 /* Check permission */</DIV>
<DIV>- bne 2f /* Bail if permission mismach */</DIV>
<DIV> </DIV>
<DIV> #ifdef CONFIG_PTE_64BIT</DIV>
<DIV>- lwz r13, 0(r12)</DIV>
<DIV>+#ifdef CONFIG_SMP</DIV>
<DIV>+ subf r10,r11,r12
/* create false data dep */</DIV>
<DIV>+ lwzx r13,r11,r10 /* Get upper pte bits */</DIV>
<DIV>+#else</DIV>
<DIV>+ lwz r13,0(r12) /* Get upper pte bits */</DIV>
<DIV>+#endif</DIV>
<DIV> #endif</DIV>
<DIV> </DIV>
<DIV>- /* Jump to common tlb load */</DIV>
<DIV>+ bne 2f
/* Bail if permission/valid mismach */</DIV>
<DIV>+</DIV>
<DIV>+ /* Jump to common tlb load */</DIV>
<DIV> b finish_tlb_load</DIV>
<DIV> 2:</DIV>
<DIV>
/* The bailout. Restore registers to pre-exception conditions</DIV>
<DIV>@@ -640,10 +646,20 @@ interrupt_base:</DIV>
<DIV> </DIV>
<DIV> FIND_PTE</DIV>
<DIV> andc. r13,r13,r11 /* Check permission */</DIV>
<DIV>+</DIV>
<DIV>+#ifdef CONFIG_PTE_64BIT</DIV>
<DIV>+#ifdef CONFIG_SMP</DIV>
<DIV>+ subf r10,r11,r12
/* create false data dep */</DIV>
<DIV>+ lwzx r13,r11,r10 /* Get upper pte bits */</DIV>
<DIV>+#else</DIV>
<DIV>+ lwz r13,0(r12) /* Get upper pte bits */</DIV>
<DIV>+#endif</DIV>
<DIV>+#endif</DIV>
<DIV>+</DIV>
<DIV> bne 2f
/* Bail if permission mismach */</DIV>
<DIV> </DIV>
<DIV> #ifdef CONFIG_PTE_64BIT</DIV>
<DIV>- lwz r13, 0(r12)</DIV>
<DIV>+ lwz r13,0(r12)</DIV>
<DIV> #endif</DIV>
<DIV> </DIV>
<DIV>
/* Jump to common TLB load point */</DIV>
<DIV>@@ -702,7 +718,7 @@ interrupt_base:</DIV>
<DIV> /*</DIV>
<DIV> * Both the instruction and data TLB miss get to this</DIV>
<DIV> * point to load the TLB.</DIV>
<DIV>- * r10 - EA of fault</DIV>
<DIV>+ * r10 - available to use</DIV>
<DIV> *
r11 - TLB (info from Linux PTE)</DIV>
<DIV> * r12 - available to use</DIV>
<DIV> *
r13 - upper bits of PTE (if PTE_64BIT) or available to use</DIV>
<DIV>-- </DIV>
<DIV>1.5.5.1</DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>------------------------------</DIV>
<DIV> </DIV>
<DIV>Message: 3</DIV>
<DIV>Date: Wed, 17 Sep 2008 18:00:05 -0500</DIV>
<DIV>From: Kumar Gala <galak@kernel.crashing.org ></DIV>
<DIV>Subject: [PATCH v7 4/4] powerpc/mm: Implement _PAGE_SPECIAL &</DIV>
<DIV>pte_special() for 32-bit</DIV>
<DIV>To: linuxppc-dev@ozlabs.org</DIV>
<DIV>Message-ID:</DIV>
<DIV><1221692405-19880-4-git-send-email-galak@kernel.crashing.org ></DIV>
<DIV> </DIV>
<DIV>Implement _PAGE_SPECIAL and pte_special() for 32-bit powerpc. This bit will</DIV>
<DIV>be used by the fast get_user_pages() to differenciate PTEs that correspond</DIV>
<DIV>to a valid struct page from special mappings that don't such as IO mappings</DIV>
<DIV>obtained via io_remap_pfn_ranges().</DIV>
<DIV> </DIV>
<DIV>We currently only implement this on sub-arch that support SMP or will so</DIV>
<DIV>in the future (6xx, 44x, FSL-BookE) and not (8xx, 40x).</DIV>
<DIV> </DIV>
<DIV>Signed-off-by: Kumar Gala <galak@kernel.crashing.org
></DIV>
<DIV>Acked-by: Benjamin Herrenschmidt
<benh@kernel.crashing.org ></DIV>
<DIV>---</DIV>
<DIV> arch/powerpc/include/asm/pgtable-ppc32.h | 15 +++++++++++++--</DIV>
<DIV> 1 files changed, 13 insertions(+), 2 deletions(-)</DIV>
<DIV> </DIV>
<DIV>diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h</DIV>
<DIV>index d1d23b9..e8f31a5 100644</DIV>
<DIV>--- a/arch/powerpc/include/asm/pgtable-ppc32.h</DIV>
<DIV>+++ b/arch/powerpc/include/asm/pgtable-ppc32.h</DIV>
<DIV>@@ -261,6 +261,7 @@ extern int icache_44x_need_flush;</DIV>
<DIV> #define _PAGE_HWEXEC 0x00000004
/* H: Execute permission */</DIV>
<DIV> #define _PAGE_ACCESSED 0x00000008
/* S: Page referenced */</DIV>
<DIV> #define _PAGE_DIRTY 0x00000010
/* S: Page dirty */</DIV>
<DIV>+#define _PAGE_SPECIAL 0x00000020
/* S: Special page */</DIV>
<DIV> #define _PAGE_USER 0x00000040
/* S: User page */</DIV>
<DIV> #define _PAGE_ENDIAN 0x00000080
/* H: E bit */</DIV>
<DIV> #define _PAGE_GUARDED 0x00000100
/* H: G bit */</DIV>
<DIV>@@ -276,6 +277,7 @@ extern int icache_44x_need_flush;</DIV>
<DIV> /* ERPN in a PTE never gets cleared, ignore it */</DIV>
<DIV> #define _PTE_NONE_MASK 0xffffffff00000000ULL</DIV>
<DIV> </DIV>
<DIV>+#define __HAVE_ARCH_PTE_SPECIAL</DIV>
<DIV> </DIV>
<DIV> #elif defined(CONFIG_FSL_BOOKE)</DIV>
<DIV> /*</DIV>
<DIV>@@ -305,6 +307,7 @@ extern int icache_44x_need_flush;</DIV>
<DIV> #define _PAGE_COHERENT 0x00100
/* H: M bit */</DIV>
<DIV> #define _PAGE_NO_CACHE 0x00200
/* H: I bit */</DIV>
<DIV> #define _PAGE_WRITETHRU 0x00400
/* H: W bit */</DIV>
<DIV>+#define _PAGE_SPECIAL
0x00800 /* S: Special page */</DIV>
<DIV> </DIV>
<DIV> #ifdef CONFIG_PTE_64BIT</DIV>
<DIV> /* ERPN in a PTE never gets cleared, ignore it */</DIV>
<DIV>@@ -315,6 +318,8 @@ extern int icache_44x_need_flush;</DIV>
<DIV> #define _PMD_PRESENT_MASK (PAGE_MASK)</DIV>
<DIV> #define _PMD_BAD (~PAGE_MASK)</DIV>
<DIV> </DIV>
<DIV>+#define __HAVE_ARCH_PTE_SPECIAL</DIV>
<DIV>+</DIV>
<DIV> #elif defined(CONFIG_8xx)</DIV>
<DIV> /* Definitions for 8xx embedded chips. */</DIV>
<DIV> #define _PAGE_PRESENT 0x0001
/* Page is valid */</DIV>
<DIV>@@ -362,6 +367,7 @@ extern int icache_44x_need_flush;</DIV>
<DIV> #define _PAGE_ACCESSED 0x100
/* R: page referenced */</DIV>
<DIV> #define _PAGE_EXEC 0x200
/* software: i-cache coherency required */</DIV>
<DIV> #define _PAGE_RW 0x400
/* software: user write access allowed */</DIV>
<DIV>+#define _PAGE_SPECIAL 0x800
/* software: Special page */</DIV>
<DIV> </DIV>
<DIV> #define _PTE_NONE_MASK _PAGE_HASHPTE</DIV>
<DIV> </DIV>
<DIV>@@ -372,6 +378,8 @@ extern int icache_44x_need_flush;</DIV>
<DIV> /* Hash table based platforms need atomic updates of the linux PTE */</DIV>
<DIV> #define PTE_ATOMIC_UPDATES 1</DIV>
<DIV> </DIV>
<DIV>+#define __HAVE_ARCH_PTE_SPECIAL</DIV>
<DIV>+</DIV>
<DIV> #endif</DIV>
<DIV> </DIV>
<DIV> /*</DIV>
<DIV>@@ -404,6 +412,9 @@ extern int icache_44x_need_flush;</DIV>
<DIV> #ifndef _PAGE_WRITETHRU</DIV>
<DIV> #define _PAGE_WRITETHRU 0</DIV>
<DIV> #endif</DIV>
<DIV>+#ifndef _PAGE_SPECIAL</DIV>
<DIV>+#define _PAGE_SPECIAL 0</DIV>
<DIV>+#endif</DIV>
<DIV> #ifndef _PMD_PRESENT_MASK</DIV>
<DIV> #define _PMD_PRESENT_MASK _PMD_PRESENT</DIV>
<DIV> #endif</DIV>
<DIV>@@ -534,7 +545,7 @@ static inline int pte_write(pte_t pte)
{ return pte_val(pte) & _PAGE_RW; }</DIV>
<DIV> static inline int pte_dirty(pte_t pte)
{ return pte_val(pte) & _PAGE_DIRTY; }</DIV>
<DIV> static inline int pte_young(pte_t pte)
{ return pte_val(pte) & _PAGE_ACCESSED; }</DIV>
<DIV> static inline int pte_file(pte_t pte)
{ return pte_val(pte) & _PAGE_FILE; }</DIV>
<DIV>-static inline int pte_special(pte_t pte)
{ return 0; }</DIV>
<DIV>+static inline int pte_special(pte_t pte)
{ return pte_val(pte) & _PAGE_SPECIAL; }</DIV>
<DIV> </DIV>
<DIV> static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }</DIV>
<DIV> static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }</DIV>
<DIV>@@ -553,7 +564,7 @@ static inline pte_t pte_mkdirty(pte_t pte) {</DIV>
<DIV> static inline pte_t pte_mkyoung(pte_t pte) {</DIV>
<DIV>
pte_val(pte) |= _PAGE_ACCESSED; return pte; }</DIV>
<DIV> static inline pte_t pte_mkspecial(pte_t pte) {</DIV>
<DIV>- return pte; }</DIV>
<DIV>+
pte_val(pte) |= _PAGE_SPECIAL; return pte; }</DIV>
<DIV> static inline unsigned long pte_pgprot(pte_t pte)</DIV>
<DIV> {</DIV>
<DIV>
return __pgprot(pte_val(pte)) & PAGE_PROT_BITS;</DIV>
<DIV>-- </DIV>
<DIV>1.5.5.1</DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>------------------------------</DIV>
<DIV> </DIV>
<DIV>_______________________________________________</DIV>
<DIV>Linuxppc-dev mailing list</DIV>
<DIV>Linuxppc-dev@ozlabs.org</DIV>
<DIV>https://ozlabs.org/mailman/listinfo/linuxppc-dev</DIV>
<DIV> </DIV>
<DIV>End of Linuxppc-dev Digest, Vol 49, Issue 89</DIV>
<DIV>********************************************</DIV></FONT></DIV></BODY></HTML>