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<p><tt>Paul Mackerras <paulus@samba.org> wrote on 05/15/2008 06:02:03 PM:<br>
<br>
> Corey J Ashford writes:<br>
> <br>
> > Thanks for the feedback. I don't believe I need a separate flag, because<br>
> > the PMU interrupt (via the PMAO bit) will still be pending when interrupts<br>
> > are hard enabled again, and the handler will be reentered automatically.<br>
> <br>
> If that were the case then we wouldn't have had the problem with<br>
> losing PMU interrupts that meant we had to change the PMU interrupt<br>
> handler from a MASKABLE_EXCEPTION to a STD_EXCEPTION. This was in<br>
> commit 449d846dbcbf61bdf7d50a923e4791102168c292.<br>
> <br>
> My understanding is that the PMU only requests an interrupt when PMAO<br>
> goes from 0 to 1 (i.e. it's edge-triggered). If the CPU takes the<br>
> interrupt and then sets MSR.EE again (e.g. by returning from the<br>
> interrupt handler), and PMAO has not been reset to 0, then I don't<br>
> think the PMU requests another interrupt at that point.<br>
> <br>
</tt><br>
<tt>I went back and looked through my notes, and found that the problem with looping in the interrupt handler I had a couple of months ago was not with PMAO not being cleared, but because there were unused counters (PMC5 and/or PMC6) were not zeroed out in the interrupt handler and so they continued to count past 0x80000000, causing PMAO to become asserted on every count. This was on POWER5+, and so the behavior may be different on other chips. I do find it a little odd that it would set PMAO on every count past 0x80000000, instead of just on the transition from 0x7fffffff to 0x80000000.</tt><br>
<br>
<tt>In any case, I do need to save the fact that an interrupt occurred and to reassert the interrupt in local_irq_restore (it appears to be the case that raw_local_irq_restore for POWER is new in 2.6.26. I'm working on 2.6.25 at the moment)</tt><br>
<br>
<tt>Thanks for your reply, as it could have taken me a long time to find this problem otherwise.</tt><br>
<br>
<tt>- Corey</tt><br>
<br>
<tt>Corey Ashford<br>
Software Engineer<br>
IBM Linux Technology Center, Linux Toolchain<br>
Beaverton, OR <br>
503-578-3507 <br>
cjashfor@us.ibm.com<br>
</tt></body></html>