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<p>Just FYI: I just tried out the code I suggested below, and it does not work; it results in a system hang. I have spent some time analyzing why this doesn't work as I expected, but so far I haven't been able to figure it out.<br>
<br>
Regards,<br>
<br>
Corey Ashford<br>
Software Engineer<br>
IBM Linux Technology Center, Linux Toolchain<br>
Beaverton, OR <br>
503-578-3507 <br>
cjashfor@us.ibm.com<br>
<br>
<br>
<tt>linuxppc-dev-bounces+cjashfor=us.ibm.com@ozlabs.org wrote on 05/15/2008 12:41:55 PM:<br>
<br>
> Hi Benjamin and Olaf,<br>
> <br>
> Thanks for the suggestions.<br>
> <br>
> Ideally, what I'm looking for is something that mimics the operation<br>
> of MASKABLE_EXCEPTION_PSERIES.<br>
> I've been looking at the kernel code (entry_64.S, exception.h, <br>
> head_64.S) but am finding it quite complicated and hard to follow, <br>
> particularly in the area of interrupt disabling wrt the soft and <br>
> hard disable logic.<br>
> <br>
> My initial thought is to do something like this in the beginning of <br>
> my perfmon2 interrupt handler:<br>
> <br>
> void perfmon_pmu_int_handler(struct pt_regs *regs) {<br>
> <br>
> if (get_paca()->soft_enabled == 0) {<br>
> /* disable hardware interrupts */<br>
> get_paca()->hard_enabled = 0;<br>
> regs->msr &= ^MSR_EE;<br>
> return;<br>
> }<br>
> ...<br>
> }<br>
> <br>
> Does this seem like it might work?<br>
> <br>
> Thanks<br>
> <br>
> Corey Ashford<br>
> Software Engineer<br>
> IBM Linux Technology Center, Linux Toolchain<br>
> Beaverton, OR <br>
> 503-578-3507 <br>
> cjashfor@us.ibm.com<br>
> <br>
> <br>
> Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote on <br>
> 05/14/2008 11:46:07 PM:<br>
> <br>
> > <br>
> > On Tue, 2008-05-13 at 15:26 -0700, Corey Ashford wrote:<br>
> > > The perfmon2 code is available here: <br>
> > > <a href="http://sourceforge.net/project/showfiles.php?group_id=144822">http://sourceforge.net/project/showfiles.php?group_id=144822</a><br>
> > > <br>
> > > perfmon2's interrupt handler does have a single entry point. Could I <br>
> > > somehow mimic what the MASKABLE_EXCEPTION_PSERIES macro does inside<br>
> > > of <br>
> > > the perfmon2 interrupt handler? Are there examples of this I can look<br>
> > > at?<br>
> > > <br>
> > > That would give us the best of both worlds.<br>
> > <br>
> > You can definitely snapshot as many data as you can, and if interrupts<br>
> > are soft-disabled, just return to the caller, storing that snapshot in<br>
> > some per-cpu data structure.<br>
> > <br>
> > You can then add something to local_irq_restore() that checks whether<br>
> > some perfmon2 stuff happened and does the actual storing of the data<br>
> > that were previously collected.<br>
> > <br>
> > Cheers,<br>
> > Ben.<br>
> > <br>
> > _______________________________________________<br>
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