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<pre>This patch add MPC52xx Interrupt controller for ARCH=powerpc.<br><br>It includes the main code in arch/powerpc/sysdev/ ad well as an header file in<br>include/asm-powerpc.<br><br>Signed-off-by: Nicolas DET <nd@bplan-gmbh.de><br>---<br>--- a/arch/powerpc/sysdev/mpc52xx_pic.c 1970-01-01 01:00:00.000000000 +0100<br>+++ b/arch/powerpc/sysdev/mpc52xx_pic.c 2006-11-06 11:10:29.000000000 +0100<br>@@ -0,0 +1,527 @@<br>+/*<br>+ *<br>+ * Programmable Interrupt Controller functions for the Freescale MPC52xx.<br>+ *<br>+ * Copyright (C) 2006 bplan GmbH<br>+ *<br>+ * Based on (well, mostly copied from) the code from the 2.4 kernel by<br>+ * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.<br>+ * <br>+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com><br>+ * Copyright (C) 2003 Montavista Software, Inc<br>+ *<br>+ * This file is licensed under the terms of the GNU General Public License<br>+ * version 2. This program is licensed "as is" without any warranty of any<br>+ * kind, whether express or implied.<br>+ *<br>+ */<br>+<br>+#undef DEBUG<br>+<br>+#include <linux/stddef.h><br>+#include <linux/init.h><br>+#include <linux/sched.h><br>+#include <linux/signal.h><br>+#include <linux/stddef.h><br>+#include <linux/delay.h><br>+#include <linux/irq.h><br>+#include <linux/hardirq.h><br>+<br>+#include <asm/io.h><br>+#include <asm/processor.h><br>+#include <asm/system.h><br>+#include <asm/irq.h><br>+#include <asm/prom.h><br>+#include <asm/mpc52xx.h><br>+<br>+/*<br>+ *<br>+*/<br>+<br>+static struct mpc52xx_intr __iomem *intr;<br>+static struct mpc52xx_sdma __iomem *sdma;<br>+static struct irq_host *mpc52xx_irqhost = NULL;<br>+<br>+static unsigned char mpc52xx_map_senses[4] = {<br>+ IRQ_TYPE_LEVEL_HIGH,<br>+ IRQ_TYPE_EDGE_RISING,<br>+ IRQ_TYPE_EDGE_FALLING,<br>+ IRQ_TYPE_LEVEL_LOW,<br>+};<br>+<br>+/*<br>+ *<br>+*/<br>+<br>+static inline void io_be_setbit(u32 __iomem *addr, int bitno)<br>+{<br>+ out_be32(addr, in_be32(addr) | (1 << bitno) );<br>+}<br>+<br>+static inline void io_be_clrbit(u32 __iomem *addr, int bitno)<br>+{<br>+ out_be32(addr, in_be32(addr) & ~(1 << bitno));<br>+}<br>+<br>+/*<br>+ * IRQ[0-3] interrupt irq_chip<br>+*/<br>+<br>+static void mpc52xx_extirq_mask(unsigned int virq)<br>+{<br>+ int irq;<br>+ int l2irq;<br>+<br>+ irq = irq_map[virq].hwirq;<br>+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;<br>+<br>+ pr_debug("%s: irq=%x. l2=%dn", __func__, irq, l2irq);<br>+<br>+ io_be_clrbit(&intr->ctrl, 11 - l2irq);<br>+}<br>+<br>+static void mpc52xx_extirq_unmask(unsigned int virq)<br>+{<br>+ int irq;<br>+ int l2irq;<br>+<br>+ irq = irq_map[virq].hwirq;<br>+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;<br>+<br>+ pr_debug("%s: irq=%x. l2=%dn", __func__, irq, l2irq);<br>+<br>+ io_be_setbit(&intr->ctrl, 11 - l2irq);<br>+}<br>+<br>+static void mpc52xx_extirq_ack(unsigned int virq)<br>+{<br>+ int irq;<br>+ int l2irq;<br>+<br>+ irq = irq_map[virq].hwirq;<br>+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;<br>+<br>+ pr_debug("%s: irq=%x. l2=%dn", __func__, irq, l2irq);<br>+<br>+ io_be_setbit(&intr->ctrl, 27-l2irq);<br>+}<br>+<br>+static struct irq_chip mpc52xx_extirq_irqchip = {<br>+ .typename = " MPC52xx IRQ[0-3] ",<br>+ .mask = mpc52xx_extirq_mask,<br>+ .unmask = mpc52xx_extirq_unmask,<br>+ .ack = mpc52xx_extirq_ack,<br>+};<br>+<br>+/*<br>+ * Main interrupt irq_chip<br>+*/<br>+<br>+static void mpc52xx_main_mask(unsigned int virq)<br>+{<br>+ int irq;<br>+ int l2irq;<br>+<br>+ irq = irq_map[virq].hwirq;<br>+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;<br>+<br>+ pr_debug("%s: irq=%x. l2=%dn", __func__, irq, l2irq);<br>+<br>+ io_be_setbit(&intr->main_mask, 15 - l2irq);<br>+}<br>+<br>+static void mpc52xx_main_unmask(unsigned int virq)<br>+{<br>+ int irq;<br>+ int l2irq;<br>+<br>+ irq = irq_map[virq].hwirq;<br>+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;<br>+<br>+ pr_debug("%s: irq=%x. l2=%dn", __func__, irq, l2irq);<br>+<br>+ io_be_clrbit(&intr->main_mask, 15 - l2irq);<br>+}<br>+<br>+static struct irq_chip mpc52xx_main_irqchip = {<br>+ .typename = "MPC52xx Main",<br>+ .mask = mpc52xx_main_mask,<br>+ .mask_ack = mpc52xx_main_mask,<br>+ .unmask = mpc52xx_main_unmask,<br>+};<br>+<br>+/*<br>+ * Peripherals interrupt irq_chip<br>+*/<br>+<br>+static void mpc52xx_periph_mask(unsigned int virq)<br>+{<br>+ int irq;<br>+ int l2irq;<br>+<br>+ irq = irq_map[virq].hwirq;<br>+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;<br>+<br>+ pr_debug("%s: irq=%x. l2=%dn", __func__, irq, l2irq);<br>+<br>+ io_be_setbit(&intr->per_mask, 31 - l2irq);<br>+}<br>+<br>+static void mpc52xx_periph_unmask(unsigned int virq)<br>+{<br>+ int irq;<br>+ int l2irq;<br>+<br>+ irq = irq_map[virq].hwirq;<br>+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;<br>+<br>+ pr_debug("%s: irq=%x. l2=%dn", __func__, irq, l2irq);<br>+<br>+ io_be_clrbit(&intr->per_mask, 31 - l2irq);<br>+}<br>+<br>+static struct irq_chip mpc52xx_periph_irqchip = {<br>+ .typename = "MPC52xx Peripherals",<br>+ .mask = mpc52xx_periph_mask,<br>+ .mask_ack = mpc52xx_periph_mask,<br>+ .unmask = mpc52xx_periph_unmask,<br>+};<br>+<br>+/*<br>+ * SDMA interrupt irq_chip<br>+*/<br>+<br>+static void mpc52xx_sdma_mask(unsigned int virq)<br>+{<br>+ int irq;<br>+ int l2irq;<br>+<br>+ irq = irq_map[virq].hwirq;<br>+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;<br>+<br>+ pr_debug("%s: irq=%x. l2=%dn", __func__, irq, l2irq);<br>+<br>+ io_be_setbit(&sdma->IntMask, l2irq);<br>+}<br>+<br>+static void mpc52xx_sdma_unmask(unsigned int virq)<br>+{<br>+ int irq;<br>+ int l2irq;<br>+<br>+ irq = irq_map[virq].hwirq;<br>+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;<br>+<br>+ pr_debug("%s: irq=%x. l2=%dn", __func__, irq, l2irq);<br>+<br>+ io_be_clrbit(&sdma->IntMask, l2irq);<br>+}<br>+<br>+static void mpc52xx_sdma_ack(unsigned int virq)<br>+{<br>+ int irq;<br>+ int l2irq;<br>+<br>+ irq = irq_map[virq].hwirq;<br>+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;<br>+<br>+ pr_debug("%s: irq=%x. l2=%dn", __func__, irq, l2irq);<br>+<br>+ out_be32(&sdma->IntPend, 1 << l2irq);<br>+}<br>+<br>+static struct irq_chip mpc52xx_sdma_irqchip = {<br>+ .typename = "MPC52xx SDMA",<br>+ .mask = mpc52xx_sdma_mask,<br>+ .unmask = mpc52xx_sdma_unmask,<br>+ .ack = mpc52xx_sdma_ack,<br>+};<br>+<br>+/*<br>+ * irq_host<br>+*/<br>+<br>+static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *node)<br>+{<br>+ pr_debug("%s: node=%pn", __func__, node);<br>+ return mpc52xx_irqhost->host_data == node;<br>+}<br>+<br>+static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,<br>+ u32 * intspec, unsigned int intsize,<br>+ irq_hw_number_t * out_hwirq,<br>+ unsigned int *out_flags)<br>+{<br>+ int intrvect_l1;<br>+ int intrvect_l2;<br>+ int intrvect_type;<br>+ int intrvect_linux;<br>+<br>+ if (intsize != 3)<br>+ return -1;<br>+<br>+ intrvect_l1 = (int)intspec[0];<br>+ intrvect_l2 = (int)intspec[1];<br>+ intrvect_type = (int)intspec[2];<br>+<br>+ intrvect_linux =<br>+ (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & MPC52xx_IRQ_L1_MASK;<br>+ intrvect_linux |=<br>+ (intrvect_l2 << MPC52xx_IRQ_L2_OFFSET) & MPC52xx_IRQ_L2_MASK;<br>+<br>+ pr_debug("return %x, l1=%d, l2=%dn", intrvect_linux, intrvect_l1,<br>+ intrvect_l2);<br>+<br>+ *out_hwirq = intrvect_linux;<br>+ *out_flags = mpc52xx_map_senses[intrvect_type];<br>+<br>+ return 0;<br>+}<br>+<br>+/*<br>+ * this function retrieves the correct IRQ type out<br>+ * of the MPC regs<br>+ * Only externals IRQs needs this<br>+*/<br>+static int mpc52xx_irqx_gettype(int irq)<br>+{<br>+ int type;<br>+ u32 ctrl_reg;<br>+<br>+ ctrl_reg = in_be32(&intr->ctrl);<br>+ type = (ctrl_reg >> (22 - irq * 2)) & 0x3;<br>+<br>+ return mpc52xx_map_senses[type];<br>+}<br>+<br>+static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,<br>+ irq_hw_number_t irq)<br>+{<br>+ int l1irq;<br>+ int l2irq;<br>+ struct irq_chip *good_irqchip;<br>+ void *good_handle;<br>+ int type;<br>+<br>+ l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;<br>+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;<br>+<br>+ /*<br>+ * Most of ours IRQs will be level low<br>+ * Only external IRQs on some platform may be others<br>+ */<br>+ type = IRQ_TYPE_LEVEL_LOW;<br>+<br>+ switch (l1irq) {<br>+ case MPC52xx_IRQ_L1_CRIT:<br>+ pr_debug("%s: Critical. l2=%xn", __func__, l2irq);<br>+<br>+ BUG_ON(l2irq != 0);<br>+<br>+ type = mpc52xx_irqx_gettype(l2irq);<br>+ good_irqchip = &mpc52xx_extirq_irqchip;<br>+ break;<br>+<br>+ case MPC52xx_IRQ_L1_MAIN:<br>+ pr_debug("%s: Main IRQ[1-3] l2=%xn", __func__, l2irq);<br>+<br>+ if ((l2irq >= 1) && (l2irq <= 3)) {<br>+ type = mpc52xx_irqx_gettype(l2irq);<br>+ good_irqchip = &mpc52xx_extirq_irqchip;<br>+ } else {<br>+ good_irqchip = &mpc52xx_main_irqchip;<br>+ }<br>+ break;<br>+<br>+ case MPC52xx_IRQ_L1_PERP:<br>+ pr_debug("%s: Peripherals. l2=%xn", __func__, l2irq);<br>+ good_irqchip = &mpc52xx_periph_irqchip;<br>+ break;<br>+<br>+ case MPC52xx_IRQ_L1_SDMA:<br>+ pr_debug("%s: SDMA. l2=%xn", __func__, l2irq);<br>+ good_irqchip = &mpc52xx_sdma_irqchip;<br>+ break;<br>+<br>+ default:<br>+ pr_debug("%s: Error, unknown L1 IRQ (0x%x)n", __func__, l1irq);<br>+ printk(KERN_ERR "Unknow IRQ!n");<br>+ return -EINVAL;<br>+ }<br>+<br>+ switch (type) {<br>+ case IRQ_TYPE_EDGE_FALLING:<br>+ case IRQ_TYPE_EDGE_RISING:<br>+ good_handle = handle_edge_irq;<br>+ break;<br>+ default:<br>+ good_handle = handle_level_irq;<br>+ }<br>+<br>+ set_irq_chip_and_handler(virq, good_irqchip, good_handle);<br>+<br>+ pr_debug("%s: virq=%x, hw=%x. type=%xn", __func__, virq,<br>+ (int)irq, type);<br>+<br>+ return 0;<br>+}<br>+<br>+static struct irq_host_ops mpc52xx_irqhost_ops = {<br>+ .match = mpc52xx_irqhost_match,<br>+ .xlate = mpc52xx_irqhost_xlate,<br>+ .map = mpc52xx_irqhost_map,<br>+};<br>+<br>+/*<br>+ * init (public)<br>+*/<br>+<br>+void __init mpc52xx_init_irq(void)<br>+{<br>+ struct device_node *picnode = NULL;<br>+ int picnode_regsize;<br>+ u32 picnode_regoffset;<br>+<br>+ struct device_node *sdmanode = NULL;<br>+ int sdmanode_regsize;<br>+ u32 sdmanode_regoffset;<br>+<br>+ u64 size64;<br>+ int flags;<br>+<br>+ u32 intr_ctrl;<br>+<br>+ picnode = of_find_compatible_node(NULL, "interrupt-controller", "mpc5200-pic");<br>+ if (picnode == NULL) {<br>+ printk(KERN_ERR "MPC52xx PIC: Unable to find the interrupt controller in the OpenFirmware device treen");<br>+ goto end;<br>+ }<br>+<br>+ sdmanode = of_find_compatible_node(NULL, "dma-controller", "mpc5200-bestcomm");<br>+ if (sdmanode == NULL) {<br>+ printk(KERN_ERR "MPC52xx PIC: Unable to find the Bestcomm DMA controller device in the OpenFirmware device treen");<br>+ goto end;<br>+ }<br>+<br>+ /* Retrieve PIC ressources */<br>+ picnode_regoffset = (u32) of_get_address(picnode, 0, &size64, &flags);<br>+ if (picnode_regoffset == 0) {<br>+ printk(KERN_ERR "MPC52xx PIC: Unable to get the interrupt controller addressn");<br>+ goto end;<br>+ }<br>+<br>+ picnode_regoffset = of_translate_address(picnode, (u32 *) picnode_regoffset);<br>+ picnode_regsize = (int) size64; <br>+<br>+ /* Retrieve SDMA ressources */<br>+ sdmanode_regoffset = (u32) of_get_address(sdmanode, 0, &size64, &flags);<br>+ if (sdmanode_regoffset == 0) {<br>+ printk(KERN_ERR "MPC52xx PIC: Unable to get the Bestcomm DMA controller addressn");<br>+ goto end;<br>+ }<br>+<br>+ sdmanode_regoffset = of_translate_address(sdmanode, (u32 *) sdmanode_regoffset);<br>+ sdmanode_regsize = (int) size64;<br>+<br>+ /* Remap the necessary zones */<br>+ intr = ioremap(picnode_regoffset, picnode_regsize);<br>+ if (intr == NULL) {<br>+ printk(KERN_ERR "MPC52xx PIC: Unable to ioremap interrupt controller registers!");<br>+ goto end;<br>+ }<br>+<br>+ sdma = ioremap(sdmanode_regoffset, sdmanode_regsize);<br>+ if (sdma == NULL) {<br>+ iounmap(intr);<br>+ printk(KERN_ERR "MPC52xx PIC: Unable to ioremap Bestcomm DMA controller registers!");<br>+ goto end;<br>+ }<br>+<br>+ printk(KERN_INFO "MPC52xx PIC: MPC52xx PIC Remapped at 0x%8.8xn", picnode_regoffset);<br>+ printk(KERN_INFO "MPC52xx PIC: MPC52xx SDMA Remapped at 0x%8.8xn", sdmanode_regoffset);<br>+<br>+ /* Disable all interrupt sources. */<br>+ out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */<br>+ out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */<br>+ out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */<br>+ out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */<br>+ intr_ctrl = in_be32(&intr->ctrl);<br>+ intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */<br>+ intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */<br>+ 0x00001000 | /* MEE master external enable */<br>+ 0x00000000 | /* 0 means disable IRQ 0-3 */<br>+ 0x00000001; /* CEb route critical normally */<br>+ out_be32(&intr->ctrl, intr_ctrl);<br>+<br>+ /* Zero a bunch of the priority settings. */<br>+ out_be32(&intr->per_pri1, 0);<br>+ out_be32(&intr->per_pri2, 0);<br>+ out_be32(&intr->per_pri3, 0);<br>+ out_be32(&intr->main_pri1, 0);<br>+ out_be32(&intr->main_pri2, 0);<br>+<br>+ /*<br>+ * As last step, add an irq host to translate the real<br>+ * hw irq information provided by the ofw to linux virq<br>+ */<br>+<br>+ mpc52xx_irqhost =<br>+ irq_alloc_host(IRQ_HOST_MAP_LINEAR, MPC52xx_IRQ_HIGHTESTHWIRQ,<br>+ &mpc52xx_irqhost_ops, -1);<br>+<br>+ if (mpc52xx_irqhost) {<br>+ mpc52xx_irqhost->host_data = picnode;<br>+ printk(KERN_INFO "MPC52xx PIC is up and running!n");<br>+ } else {<br>+ printk(KERN_ERR "MPC52xx PIC: Unable to allocate the IRQ hostn");<br>+ }<br>+<br>+end:<br>+ of_node_put(picnode);<br>+ of_node_put(sdmanode);<br>+}<br>+<br>+/*<br>+ * get_irq (public)<br>+*/<br>+unsigned int mpc52xx_get_irq(void)<br>+{<br>+ u32 status;<br>+ int irq = NO_IRQ_IGNORE;<br>+<br>+ status = in_be32(&intr->enc_status);<br>+ if (status & 0x00000400) { /* critical */<br>+ irq = (status >> 8) & 0x3;<br>+ if (irq == 2) /* high priority peripheral */<br>+ goto peripheral;<br>+ irq |=<br>+ (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET) &<br>+ MPC52xx_IRQ_L1_MASK;<br>+ } else if (status & 0x00200000) { /* main */<br>+ irq = (status >> 16) & 0x1f;<br>+ if (irq == 4) /* low priority peripheral */<br>+ goto peripheral;<br>+ irq |=<br>+ (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET) &<br>+ MPC52xx_IRQ_L1_MASK;<br>+ } else if (status & 0x20000000) { /* peripheral */<br>+ peripheral:<br>+ irq = (status >> 24) & 0x1f;<br>+ if (irq == 0) { /* bestcomm */<br>+ status = in_be32(&sdma->IntPend);<br>+ irq = ffs(status) - 1;<br>+ irq |=<br>+ (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET) &<br>+ MPC52xx_IRQ_L1_MASK;<br>+ } else<br>+ irq |=<br>+ (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET) &<br>+ MPC52xx_IRQ_L1_MASK;<br>+<br>+ }<br>+<br>+ pr_debug("%s: irq=%x. virq=%dn", __func__, irq,<br>+ irq_linear_revmap(mpc52xx_irqhost, irq));<br>+<br>+ return irq_linear_revmap(mpc52xx_irqhost, irq);<br>+}<br>--- a/arch/powerpc/sysdev/Makefile 2006-11-01 09:18:43.000000000 +0100<br>+++ b/arch/powerpc/sysdev/Makefile 2006-11-06 11:10:46.000000000 +0100<br>@@ -13,6 +13,7 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o<br> obj-$(CONFIG_PPC_TODC) += todc.o<br> obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o<br> obj-$(CONFIG_QUICC_ENGINE) += qe_lib/<br>+obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_pic.o<br> <br> ifeq ($(CONFIG_PPC_MERGE),y)<br> obj-$(CONFIG_PPC_I8259) += i8259.o<br>--- a/include/asm-powerpc/mpc52xx.h 1970-01-01 01:00:00.000000000 +0100<br>+++ b/include/asm-powerpc/mpc52xx.h 2006-11-06 11:10:29.000000000 +0100<br>@@ -0,0 +1,283 @@<br>+/*<br>+ * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips<br>+ * May need to be cleaned as the port goes on ...<br>+ *<br>+ * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com><br>+ * Copyright (C) 2003 MontaVista, Software, Inc.<br>+ *<br>+ * This file is licensed under the terms of the GNU General Public License<br>+ * version 2. This program is licensed "as is" without any warranty of any<br>+ * kind, whether express or implied.<br>+ */<br>+<br>+#ifndef __ASM_POWERPC_MPC52xx_H__<br>+#define __ASM_POWERPC_MPC52xx_H__<br>+<br>+#ifndef __ASSEMBLY__<br>+#include <asm/types.h><br>+#include <asm/prom.h><br>+#endif /* __ASSEMBLY__ */<br>+<br>+/* HW IRQ mapping */<br>+#define MPC52xx_IRQ_L1_CRIT (0)<br>+#define MPC52xx_IRQ_L1_MAIN (1)<br>+#define MPC52xx_IRQ_L1_PERP (2)<br>+#define MPC52xx_IRQ_L1_SDMA (3)<br>+<br>+#define MPC52xx_IRQ_L1_OFFSET (6)<br>+#define MPC52xx_IRQ_L1_MASK (0xc0)<br>+<br>+#define MPC52xx_IRQ_L2_OFFSET (0)<br>+#define MPC52xx_IRQ_L2_MASK (0x3f)<br>+<br>+#define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)<br>+<br>+/* Interrupt controller Register set */<br>+struct mpc52xx_intr {<br>+ u32 per_mask; /* INTR + 0x00 */<br>+ u32 per_pri1; /* INTR + 0x04 */<br>+ u32 per_pri2; /* INTR + 0x08 */<br>+ u32 per_pri3; /* INTR + 0x0c */<br>+ u32 ctrl; /* INTR + 0x10 */<br>+ u32 main_mask; /* INTR + 0x14 */<br>+ u32 main_pri1; /* INTR + 0x18 */<br>+ u32 main_pri2; /* INTR + 0x1c */<br>+ u32 reserved1; /* INTR + 0x20 */<br>+ u32 enc_status; /* INTR + 0x24 */<br>+ u32 crit_status; /* INTR + 0x28 */<br>+ u32 main_status; /* INTR + 0x2c */<br>+ u32 per_status; /* INTR + 0x30 */<br>+ u32 reserved2; /* INTR + 0x34 */<br>+ u32 per_error; /* INTR + 0x38 */<br>+};<br>+<br>+<br>+/* ======================================================================== */<br>+/* Structures mapping of some unit register set */<br>+/* ======================================================================== */<br>+<br>+#ifndef __ASSEMBLY__<br>+<br>+/* Memory Mapping Control */<br>+struct mpc52xx_mmap_ctl {<br>+ u32 mbar; /* MMAP_CTRL + 0x00 */<br>+<br>+ u32 cs0_start; /* MMAP_CTRL + 0x04 */<br>+ u32 cs0_stop; /* MMAP_CTRL + 0x08 */<br>+ u32 cs1_start; /* MMAP_CTRL + 0x0c */<br>+ u32 cs1_stop; /* MMAP_CTRL + 0x10 */<br>+ u32 cs2_start; /* MMAP_CTRL + 0x14 */<br>+ u32 cs2_stop; /* MMAP_CTRL + 0x18 */<br>+ u32 cs3_start; /* MMAP_CTRL + 0x1c */<br>+ u32 cs3_stop; /* MMAP_CTRL + 0x20 */<br>+ u32 cs4_start; /* MMAP_CTRL + 0x24 */<br>+ u32 cs4_stop; /* MMAP_CTRL + 0x28 */<br>+ u32 cs5_start; /* MMAP_CTRL + 0x2c */<br>+ u32 cs5_stop; /* MMAP_CTRL + 0x30 */<br>+<br>+ u32 sdram0; /* MMAP_CTRL + 0x34 */<br>+ u32 sdram1; /* MMAP_CTRL + 0X38 */<br>+<br>+ u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */<br>+<br>+ u32 boot_start; /* MMAP_CTRL + 0x4c */<br>+ u32 boot_stop; /* MMAP_CTRL + 0x50 */<br>+<br>+ u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */<br>+<br>+ u32 cs6_start; /* MMAP_CTRL + 0x58 */<br>+ u32 cs6_stop; /* MMAP_CTRL + 0x5c */<br>+ u32 cs7_start; /* MMAP_CTRL + 0x60 */<br>+ u32 cs7_stop; /* MMAP_CTRL + 0x64 */<br>+};<br>+<br>+/* SDRAM control */<br>+struct mpc52xx_sdram {<br>+ u32 mode; /* SDRAM + 0x00 */<br>+ u32 ctrl; /* SDRAM + 0x04 */<br>+ u32 config1; /* SDRAM + 0x08 */<br>+ u32 config2; /* SDRAM + 0x0c */<br>+};<br>+<br>+/* SDMA */<br>+struct mpc52xx_sdma {<br>+ u32 taskBar; /* SDMA + 0x00 */<br>+ u32 currentPointer; /* SDMA + 0x04 */<br>+ u32 endPointer; /* SDMA + 0x08 */<br>+ u32 variablePointer; /* SDMA + 0x0c */<br>+<br>+ u8 IntVect1; /* SDMA + 0x10 */<br>+ u8 IntVect2; /* SDMA + 0x11 */<br>+ u16 PtdCntrl; /* SDMA + 0x12 */<br>+<br>+ u32 IntPend; /* SDMA + 0x14 */<br>+ u32 IntMask; /* SDMA + 0x18 */<br>+<br>+ u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */<br>+<br>+ u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */<br>+<br>+ u32 cReqSelect; /* SDMA + 0x5c */<br>+ u32 task_size0; /* SDMA + 0x60 */<br>+ u32 task_size1; /* SDMA + 0x64 */<br>+ u32 MDEDebug; /* SDMA + 0x68 */<br>+ u32 ADSDebug; /* SDMA + 0x6c */<br>+ u32 Value1; /* SDMA + 0x70 */<br>+ u32 Value2; /* SDMA + 0x74 */<br>+ u32 Control; /* SDMA + 0x78 */<br>+ u32 Status; /* SDMA + 0x7c */<br>+ u32 PTDDebug; /* SDMA + 0x80 */<br>+};<br>+<br>+/* GPT */<br>+struct mpc52xx_gpt {<br>+ u32 mode; /* GPTx + 0x00 */<br>+ u32 count; /* GPTx + 0x04 */<br>+ u32 pwm; /* GPTx + 0x08 */<br>+ u32 status; /* GPTx + 0X0c */<br>+};<br>+<br>+/* GPIO */<br>+struct mpc52xx_gpio {<br>+ u32 port_config; /* GPIO + 0x00 */<br>+ u32 simple_gpioe; /* GPIO + 0x04 */<br>+ u32 simple_ode; /* GPIO + 0x08 */<br>+ u32 simple_ddr; /* GPIO + 0x0c */<br>+ u32 simple_dvo; /* GPIO + 0x10 */<br>+ u32 simple_ival; /* GPIO + 0x14 */<br>+ u8 outo_gpioe; /* GPIO + 0x18 */<br>+ u8 reserved1[3]; /* GPIO + 0x19 */<br>+ u8 outo_dvo; /* GPIO + 0x1c */<br>+ u8 reserved2[3]; /* GPIO + 0x1d */<br>+ u8 sint_gpioe; /* GPIO + 0x20 */<br>+ u8 reserved3[3]; /* GPIO + 0x21 */<br>+ u8 sint_ode; /* GPIO + 0x24 */<br>+ u8 reserved4[3]; /* GPIO + 0x25 */<br>+ u8 sint_ddr; /* GPIO + 0x28 */<br>+ u8 reserved5[3]; /* GPIO + 0x29 */<br>+ u8 sint_dvo; /* GPIO + 0x2c */<br>+ u8 reserved6[3]; /* GPIO + 0x2d */<br>+ u8 sint_inten; /* GPIO + 0x30 */<br>+ u8 reserved7[3]; /* GPIO + 0x31 */<br>+ u16 sint_itype; /* GPIO + 0x34 */<br>+ u16 reserved8; /* GPIO + 0x36 */<br>+ u8 gpio_control; /* GPIO + 0x38 */<br>+ u8 reserved9[3]; /* GPIO + 0x39 */<br>+ u8 sint_istat; /* GPIO + 0x3c */<br>+ u8 sint_ival; /* GPIO + 0x3d */<br>+ u8 bus_errs; /* GPIO + 0x3e */<br>+ u8 reserved10; /* GPIO + 0x3f */<br>+};<br>+<br>+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4<br>+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5<br>+#define MPC52xx_GPIO_PCI_DIS (1<<15)<br>+<br>+/* GPIO with WakeUp*/<br>+struct mpc52xx_gpio_wkup {<br>+ u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */<br>+ u8 reserved1[3]; /* GPIO_WKUP + 0x03 */<br>+ u8 wkup_ode; /* GPIO_WKUP + 0x04 */<br>+ u8 reserved2[3]; /* GPIO_WKUP + 0x05 */<br>+ u8 wkup_ddr; /* GPIO_WKUP + 0x08 */<br>+ u8 reserved3[3]; /* GPIO_WKUP + 0x09 */<br>+ u8 wkup_dvo; /* GPIO_WKUP + 0x0C */<br>+ u8 reserved4[3]; /* GPIO_WKUP + 0x0D */<br>+ u8 wkup_inten; /* GPIO_WKUP + 0x10 */<br>+ u8 reserved5[3]; /* GPIO_WKUP + 0x11 */<br>+ u8 wkup_iinten; /* GPIO_WKUP + 0x14 */<br>+ u8 reserved6[3]; /* GPIO_WKUP + 0x15 */<br>+ u16 wkup_itype; /* GPIO_WKUP + 0x18 */<br>+ u8 reserved7[2]; /* GPIO_WKUP + 0x1A */<br>+ u8 wkup_maste; /* GPIO_WKUP + 0x1C */<br>+ u8 reserved8[3]; /* GPIO_WKUP + 0x1D */<br>+ u8 wkup_ival; /* GPIO_WKUP + 0x20 */<br>+ u8 reserved9[3]; /* GPIO_WKUP + 0x21 */<br>+ u8 wkup_istat; /* GPIO_WKUP + 0x24 */<br>+ u8 reserved10[3]; /* GPIO_WKUP + 0x25 */<br>+};<br>+<br>+/* XLB Bus control */<br>+struct mpc52xx_xlb {<br>+ u8 reserved[0x40];<br>+ u32 config; /* XLB + 0x40 */<br>+ u32 version; /* XLB + 0x44 */<br>+ u32 status; /* XLB + 0x48 */<br>+ u32 int_enable; /* XLB + 0x4c */<br>+ u32 addr_capture; /* XLB + 0x50 */<br>+ u32 bus_sig_capture; /* XLB + 0x54 */<br>+ u32 addr_timeout; /* XLB + 0x58 */<br>+ u32 data_timeout; /* XLB + 0x5c */<br>+ u32 bus_act_timeout; /* XLB + 0x60 */<br>+ u32 master_pri_enable; /* XLB + 0x64 */<br>+ u32 master_priority; /* XLB + 0x68 */<br>+ u32 base_address; /* XLB + 0x6c */<br>+ u32 snoop_window; /* XLB + 0x70 */<br>+};<br>+<br>+#define MPC52xx_XLB_CFG_PLDIS (1 << 31)<br>+#define MPC52xx_XLB_CFG_SNOOP (1 << 15)<br>+<br>+/* Clock Distribution control */<br>+struct mpc52xx_cdm {<br>+ u32 jtag_id; /* CDM + 0x00 reg0 read only */<br>+ u32 rstcfg; /* CDM + 0x04 reg1 read only */<br>+ u32 breadcrumb; /* CDM + 0x08 reg2 */<br>+<br>+ u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */<br>+ u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */<br>+ u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */<br>+ u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */<br>+<br>+ u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */<br>+ u8 fd_enable; /* CDM + 0x11 reg4 byte1 */<br>+ u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */<br>+<br>+ u32 clk_enables; /* CDM + 0x14 reg5 */<br>+<br>+ u8 osc_disable; /* CDM + 0x18 reg6 byte0 */<br>+ u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */<br>+<br>+ u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */<br>+ u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */<br>+ u8 reserved1; /* CDM + 0x1e reg7 byte2 */<br>+ u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */<br>+<br>+ u8 soft_reset; /* CDM + 0x20 u8 byte0 */<br>+ u8 no_ckstp; /* CDM + 0x21 u8 byte0 */<br>+ u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */<br>+<br>+ u8 pll_lock; /* CDM + 0x24 reg9 byte0 */<br>+ u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */<br>+ u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */<br>+ u8 reserved3; /* CDM + 0x27 reg9 byte3 */<br>+<br>+ u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */<br>+ u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */<br>+<br>+ u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */<br>+ u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */<br>+<br>+ u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */<br>+ u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */<br>+<br>+ u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */<br>+ u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */<br>+};<br>+<br>+#endif /* __ASSEMBLY__ */<br>+<br>+<br>+/* ========================================================================= */<br>+/* Prototypes for MPC52xx sysdev */<br>+/* ========================================================================= */<br>+<br>+#ifndef __ASSEMBLY__<br>+<br>+extern void mpc52xx_init_irq(void);<br>+extern unsigned int mpc52xx_get_irq(void);<br>+<br>+#endif /* __ASSEMBLY__ */<br>+<br>+#endif /* __ASM_POWERPC_MPC52xx_H__ */<br>+<br><br></pre></BODY></HTML>