<div><br>Would you mind explain me the last question in previous email?</div>
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<div>You are not leaving any memory space for any of the onchip devices,<br>the error messages are because the regions of memory that the devices<br>are expected to be at are already occupied by the PCI space.<br> </div>
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<div><font style="BACKGROUND-COLOR: #ffffff" color="#3366ff">Isn't it the PCI IO and PCI MEM space are separated from local memory space? I think I see the global IO resource and MEM resource have the range of 0x0 - 0xFFFFFFFF.
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<div>Thanks,</div>
<div>Luong Ngo<br> </div>
<div><span class="gmail_quote">On 10/24/06, <b class="gmail_sendername">Kumar Gala</b> <<a href="mailto:galak@kernel.crashing.org">galak@kernel.crashing.org</a>> wrote:</span>
<blockquote class="gmail_quote" style="PADDING-LEFT: 1ex; MARGIN: 0px 0px 0px 0.8ex; BORDER-LEFT: #ccc 1px solid"><br>> I'm a bit confused here. If the host bridge is ignored/excluded,<br>> then the region size in BARs will not be allocated corresponding
<br>> resource by the PCI subsystem, then how would other PCI devices in<br>> the slots could be allocated in the BAR's range? If I understand<br>> correctly, the PCI devices's resources are allocated based on the
<br>> bridge resource, which is assigned statically by PCI subsystem<br>> using hose->mem_space and hose->io_space instead of reading it from<br>> the BARs. Maybe you are saying in the case the CPU is in agent mode
<br>> and its PCI host bridge is functioning as a PCI-PCI bridge?<br><br>The problem is the host bridge shouldn't be included in BAR<br>assignment since its the host bridge. The problem is FSL devices<br>show up when they scan themselves and the kernel then tries to
<br>allocate resources to them as if they were any other device.<br><br>you are correct, the pci subsystem is setup via the hose structure<br>and not by trying to read BARs on the host controller itself.<br><br>- kumar<br>
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