<div dir="ltr">Dear Kernel Maintainers,<div>I hope this email finds you well.</div><div><br></div><div>If I may ask, what do we need to do to move this patch forward?</div><div><br></div><div>Thank you for your help,</div><div>Mo</div></div><br><div class="gmail_quote gmail_quote_container"><div dir="ltr" class="gmail_attr">On Tue, Jul 8, 2025 at 11:41 PM Ryan Chen <<a href="mailto:ryan_chen@aspeedtech.com">ryan_chen@aspeedtech.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Hello Stephen,<br>
sorry to bother you, do you have time to review this patch?<br>
Ryan<br>
<br>
> -----Original Message-----<br>
> From: Ryan Chen <<a href="mailto:ryan_chen@aspeedtech.com" target="_blank">ryan_chen@aspeedtech.com</a>><br>
> Sent: Tuesday, July 8, 2025 1:29 PM<br>
> To: Ryan Chen <<a href="mailto:ryan_chen@aspeedtech.com" target="_blank">ryan_chen@aspeedtech.com</a>>; Michael Turquette<br>
> <<a href="mailto:mturquette@baylibre.com" target="_blank">mturquette@baylibre.com</a>>; Stephen Boyd <<a href="mailto:sboyd@kernel.org" target="_blank">sboyd@kernel.org</a>>; Philipp Zabel<br>
> <<a href="mailto:p.zabel@pengutronix.de" target="_blank">p.zabel@pengutronix.de</a>>; Joel Stanley <<a href="mailto:joel@jms.id.au" target="_blank">joel@jms.id.au</a>>; Andrew Jeffery<br>
> <<a href="mailto:andrew@codeconstruct.com.au" target="_blank">andrew@codeconstruct.com.au</a>>; Rob Herring <<a href="mailto:robh@kernel.org" target="_blank">robh@kernel.org</a>>; Krzysztof<br>
> Kozlowski <<a href="mailto:krzk%2Bdt@kernel.org" target="_blank">krzk+dt@kernel.org</a>>; Conor Dooley <<a href="mailto:conor%2Bdt@kernel.org" target="_blank">conor+dt@kernel.org</a>>;<br>
> <a href="mailto:linux-clk@vger.kernel.org" target="_blank">linux-clk@vger.kernel.org</a>; <a href="mailto:linux-arm-kernel@lists.infradead.org" target="_blank">linux-arm-kernel@lists.infradead.org</a>;<br>
> <a href="mailto:linux-aspeed@lists.ozlabs.org" target="_blank">linux-aspeed@lists.ozlabs.org</a>; <a href="mailto:devicetree@vger.kernel.org" target="_blank">devicetree@vger.kernel.org</a>;<br>
> <a href="mailto:linux-kernel@vger.kernel.org" target="_blank">linux-kernel@vger.kernel.org</a>; Mo Elbadry <<a href="mailto:elbadrym@google.com" target="_blank">elbadrym@google.com</a>>; Rom<br>
> Lemarchand <<a href="mailto:romlem@google.com" target="_blank">romlem@google.com</a>>; William Kennington <<a href="mailto:wak@google.com" target="_blank">wak@google.com</a>>;<br>
> Yuxiao Zhang <<a href="mailto:yuxiaozhang@google.com" target="_blank">yuxiaozhang@google.com</a>>; <a href="mailto:wthai@nvidia.com" target="_blank">wthai@nvidia.com</a>;<br>
> <a href="mailto:leohu@nvidia.com" target="_blank">leohu@nvidia.com</a>; <a href="mailto:dkodihalli@nvidia.com" target="_blank">dkodihalli@nvidia.com</a>; <a href="mailto:spuranik@nvidia.com" target="_blank">spuranik@nvidia.com</a><br>
> Subject: [PATCH v12 3/3] clk: aspeed: add AST2700 clock driver<br>
> <br>
> Add AST2700 clock controller driver and also use axiliary device framework<br>
> register the reset controller driver.<br>
> Due to clock and reset using the same register region.<br>
> <br>
> Signed-off-by: Ryan Chen <<a href="mailto:ryan_chen@aspeedtech.com" target="_blank">ryan_chen@aspeedtech.com</a>><br>
> ---<br>
> drivers/clk/Kconfig | 8 +<br>
> drivers/clk/Makefile | 1 +<br>
> drivers/clk/clk-ast2700.c | 1138<br>
> +++++++++++++++++++++++++++++++++++++<br>
> 3 files changed, 1147 insertions(+)<br>
> create mode 100644 drivers/clk/clk-ast2700.c<br>
> <br>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index<br>
> 19c1ed280fd7..10b67370f65d 100644<br>
> --- a/drivers/clk/Kconfig<br>
> +++ b/drivers/clk/Kconfig<br>
> @@ -288,6 +288,14 @@ config COMMON_CLK_ASPEED<br>
> The G4 and G5 series, including the ast2400 and ast2500, are<br>
> supported<br>
> by this driver.<br>
> <br>
> +config COMMON_CLK_AST2700<br>
> + bool "Clock driver for AST2700 SoC"<br>
> + depends on ARCH_ASPEED || COMPILE_TEST<br>
> + help<br>
> + This driver provides support for clock on AST2700 SoC.<br>
> + The driver is responsible for managing the various clocks required<br>
> + by the peripherals and cores within the AST2700.<br>
> +<br>
> config COMMON_CLK_S2MPS11<br>
> tristate "Clock driver for S2MPS1X/S5M8767 MFD"<br>
> depends on MFD_SEC_CORE || COMPILE_TEST diff --git<br>
> a/drivers/clk/Makefile b/drivers/clk/Makefile index<br>
> 42867cd37c33..3d911b81149c 100644<br>
> --- a/drivers/clk/Makefile<br>
> +++ b/drivers/clk/Makefile<br>
> @@ -63,6 +63,7 @@ obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o<br>
> obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o<br>
> obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o<br>
> obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o<br>
> +obj-$(CONFIG_COMMON_CLK_AST2700) += clk-ast2700.o<br>
> obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o<br>
> obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o<br>
> obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o<br>
> diff --git a/drivers/clk/clk-ast2700.c b/drivers/clk/clk-ast2700.c new file mode<br>
> 100644 index 000000000000..c6d77e3f4ace<br>
> --- /dev/null<br>
> +++ b/drivers/clk/clk-ast2700.c<br>
> @@ -0,0 +1,1138 @@<br>
> +// SPDX-License-Identifier: GPL-2.0<br>
> +/*<br>
> + * Copyright (c) 2024 ASPEED Technology Inc.<br>
> + * Author: Ryan Chen <<a href="mailto:ryan_chen@aspeedtech.com" target="_blank">ryan_chen@aspeedtech.com</a>> */ #include<br>
> +<linux/auxiliary_bus.h> #include <linux/bitfield.h> #include<br>
> +<linux/clk-provider.h> #include <linux/io.h> #include<br>
> +<linux/mod_devicetable.h> #include <linux/of_platform.h> #include<br>
> +<linux/platform_device.h> #include <linux/slab.h> #include<br>
> +<linux/units.h><br>
> +<br>
> +#include <dt-bindings/clock/aspeed,ast2700-scu.h><br>
> +<br>
> +#define SCU_CLK_12MHZ (12 * HZ_PER_MHZ)<br>
> +#define SCU_CLK_24MHZ (24 * HZ_PER_MHZ)<br>
> +#define SCU_CLK_25MHZ (25 * HZ_PER_MHZ)<br>
> +#define SCU_CLK_192MHZ (192 * HZ_PER_MHZ)<br>
> +<br>
> +/* SOC0 */<br>
> +#define SCU0_HWSTRAP1 0x010<br>
> +#define SCU0_CLK_STOP 0x240<br>
> +#define SCU0_CLK_SEL1 0x280<br>
> +#define SCU0_CLK_SEL2 0x284<br>
> +#define GET_USB_REFCLK_DIV(x) ((GENMASK(23, 20) & (x)) >> 20)<br>
> +#define UART_DIV13_EN BIT(30)<br>
> +#define SCU0_HPLL_PARAM 0x300<br>
> +#define SCU0_DPLL_PARAM 0x308<br>
> +#define SCU0_MPLL_PARAM 0x310<br>
> +#define SCU0_D0CLK_PARAM 0x320<br>
> +#define SCU0_D1CLK_PARAM 0x330<br>
> +#define SCU0_CRT0CLK_PARAM 0x340<br>
> +#define SCU0_CRT1CLK_PARAM 0x350<br>
> +#define SCU0_MPHYCLK_PARAM 0x360<br>
> +<br>
> +/* SOC1 */<br>
> +#define SCU1_REVISION_ID 0x0<br>
> +#define REVISION_ID GENMASK(23, 16)<br>
> +#define SCU1_CLK_STOP 0x240<br>
> +#define SCU1_CLK_STOP2 0x260<br>
> +#define SCU1_CLK_SEL1 0x280<br>
> +#define SCU1_CLK_SEL2 0x284<br>
> +#define SCU1_CLK_I3C_DIV_MASK GENMASK(25, 23)<br>
> +#define SCU1_CLK_I3C_DIV(n) ((n) - 1)<br>
> +#define UXCLK_MASK GENMASK(1, 0)<br>
> +#define HUXCLK_MASK GENMASK(4, 3)<br>
> +#define SCU1_HPLL_PARAM 0x300<br>
> +#define SCU1_APLL_PARAM 0x310<br>
> +#define SCU1_DPLL_PARAM 0x320<br>
> +#define SCU1_UXCLK_CTRL 0x330<br>
> +#define SCU1_HUXCLK_CTRL 0x334<br>
> +#define SCU1_MAC12_CLK_DLY 0x390<br>
> +#define SCU1_MAC12_CLK_DLY_100M 0x394<br>
> +#define SCU1_MAC12_CLK_DLY_10M 0x398<br>
> +<br>
> +enum ast2700_clk_type {<br>
> + CLK_MUX,<br>
> + CLK_PLL,<br>
> + CLK_HPLL,<br>
> + CLK_GATE,<br>
> + CLK_MISC,<br>
> + CLK_FIXED,<br>
> + DCLK_FIXED,<br>
> + CLK_DIVIDER,<br>
> + CLK_UART_PLL,<br>
> + CLK_FIXED_FACTOR,<br>
> + CLK_GATE_ASPEED,<br>
> +};<br>
> +<br>
> +struct ast2700_clk_fixed_factor_data {<br>
> + const struct clk_parent_data *parent;<br>
> + unsigned int mult;<br>
> + unsigned int div;<br>
> +};<br>
> +<br>
> +struct ast2700_clk_gate_data {<br>
> + const struct clk_parent_data *parent;<br>
> + u32 flags;<br>
> + u32 reg;<br>
> + u8 bit;<br>
> +};<br>
> +<br>
> +struct ast2700_clk_mux_data {<br>
> + const struct clk_parent_data *parents;<br>
> + unsigned int num_parents;<br>
> + u8 bit_shift;<br>
> + u8 bit_width;<br>
> + u32 reg;<br>
> +};<br>
> +<br>
> +struct ast2700_clk_div_data {<br>
> + const struct clk_div_table *div_table;<br>
> + const struct clk_parent_data *parent;<br>
> + u8 bit_shift;<br>
> + u8 bit_width;<br>
> + u32 reg;<br>
> +};<br>
> +<br>
> +struct ast2700_clk_pll_data {<br>
> + const struct clk_parent_data *parent;<br>
> + u32 reg;<br>
> +};<br>
> +<br>
> +struct ast2700_clk_fixed_rate_data {<br>
> + unsigned long fixed_rate;<br>
> +};<br>
> +<br>
> +struct ast2700_clk_info {<br>
> + const char *name;<br>
> + u8 clk_idx;<br>
> + u32 reg;<br>
> + u32 type;<br>
> + union {<br>
> + struct ast2700_clk_fixed_factor_data factor;<br>
> + struct ast2700_clk_fixed_rate_data rate;<br>
> + struct ast2700_clk_gate_data gate;<br>
> + struct ast2700_clk_div_data div;<br>
> + struct ast2700_clk_pll_data pll;<br>
> + struct ast2700_clk_mux_data mux;<br>
> + } data;<br>
> +};<br>
> +<br>
> +struct ast2700_clk_data {<br>
> + struct ast2700_clk_info const *clk_info;<br>
> + unsigned int nr_clks;<br>
> + const int scu;<br>
> +};<br>
> +<br>
> +struct ast2700_clk_ctrl {<br>
> + const struct ast2700_clk_data *clk_data;<br>
> + struct device *dev;<br>
> + void __iomem *base;<br>
> + spinlock_t lock; /* clk lock */<br>
> +};<br>
> +<br>
> +static const struct clk_div_table ast2700_rgmii_div_table[] = {<br>
> + { 0x0, 4 },<br>
> + { 0x1, 4 },<br>
> + { 0x2, 6 },<br>
> + { 0x3, 8 },<br>
> + { 0x4, 10 },<br>
> + { 0x5, 12 },<br>
> + { 0x6, 14 },<br>
> + { 0x7, 16 },<br>
> + { 0 }<br>
> +};<br>
> +<br>
> +static const struct clk_div_table ast2700_rmii_div_table[] = {<br>
> + { 0x0, 8 },<br>
> + { 0x1, 8 },<br>
> + { 0x2, 12 },<br>
> + { 0x3, 16 },<br>
> + { 0x4, 20 },<br>
> + { 0x5, 24 },<br>
> + { 0x6, 28 },<br>
> + { 0x7, 32 },<br>
> + { 0 }<br>
> +};<br>
> +<br>
> +static const struct clk_div_table ast2700_clk_div_table[] = {<br>
> + { 0x0, 2 },<br>
> + { 0x1, 2 },<br>
> + { 0x2, 3 },<br>
> + { 0x3, 4 },<br>
> + { 0x4, 5 },<br>
> + { 0x5, 6 },<br>
> + { 0x6, 7 },<br>
> + { 0x7, 8 },<br>
> + { 0 }<br>
> +};<br>
> +<br>
> +static const struct clk_div_table ast2700_clk_div_table2[] = {<br>
> + { 0x0, 2 },<br>
> + { 0x1, 4 },<br>
> + { 0x2, 6 },<br>
> + { 0x3, 8 },<br>
> + { 0x4, 10 },<br>
> + { 0x5, 12 },<br>
> + { 0x6, 14 },<br>
> + { 0x7, 16 },<br>
> + { 0 }<br>
> +};<br>
> +<br>
> +static const struct clk_div_table ast2700_hclk_div_table[] = {<br>
> + { 0x0, 6 },<br>
> + { 0x1, 5 },<br>
> + { 0x2, 4 },<br>
> + { 0x3, 7 },<br>
> + { 0 }<br>
> +};<br>
> +<br>
> +static const struct clk_div_table ast2700_clk_uart_div_table[] = {<br>
> + { 0x0, 1 },<br>
> + { 0x1, 13 },<br>
> + { 0 }<br>
> +};<br>
> +<br>
> +static const struct clk_parent_data soc0_clkin[] = {<br>
> + { .fw_name = "soc0-clkin", .name = "soc0-clkin" }, };<br>
> +<br>
> +static const struct clk_parent_data pspclk[] = {<br>
> + { .fw_name = "pspclk", .name = "pspclk" }, };<br>
> +<br>
> +static const struct clk_parent_data mphysrc[] = {<br>
> + { .fw_name = "mphysrc", .name = "mphysrc" }, };<br>
> +<br>
> +static const struct clk_parent_data u2phy_refclksrc[] = {<br>
> + { .fw_name = "u2phy_refclksrc", .name = "u2phy_refclksrc" }, };<br>
> +<br>
> +static const struct clk_parent_data soc0_hpll[] = {<br>
> + { .fw_name = "soc0-hpll", .name = "soc0-hpll" }, };<br>
> +<br>
> +static const struct clk_parent_data soc0_mpll[] = {<br>
> + { .fw_name = "soc0-mpll", .name = "soc0-mpll" }, };<br>
> +<br>
> +static const struct clk_parent_data axi0clk[] = {<br>
> + { .fw_name = "axi0clk", .name = "axi0clk" }, };<br>
> +<br>
> +static const struct clk_parent_data soc0_ahbmux[] = {<br>
> + { .fw_name = "soc0-ahbmux", .name = "soc0-ahbmux" }, };<br>
> +<br>
> +static const struct clk_parent_data soc0_uartclk[] = {<br>
> + { .fw_name = "soc0-uartclk", .name = "soc0-uartclk" }, };<br>
> +<br>
> +static const struct clk_parent_data emmcclk[] = {<br>
> + { .fw_name = "emmcclk", .name = "emmcclk" }, };<br>
> +<br>
> +static const struct clk_parent_data emmcsrc_mux[] = {<br>
> + { .fw_name = "emmcsrc-mux", .name = "emmcsrc-mux" }, };<br>
> +<br>
> +static const struct clk_parent_data soc1_clkin[] = {<br>
> + { .fw_name = "soc1-clkin", .name = "soc1-clkin" }, };<br>
> +<br>
> +static const struct clk_parent_data soc1_hpll[] = {<br>
> + { .fw_name = "soc1-hpll", .name = "soc1-hpll" }, };<br>
> +<br>
> +static const struct clk_parent_data soc1_apll[] = {<br>
> + { .fw_name = "soc1-apll", .name = "soc1-apll" }, };<br>
> +<br>
> +static const struct clk_parent_data sdclk[] = {<br>
> + { .fw_name = "sdclk", .name = "sdclk" }, };<br>
> +<br>
> +static const struct clk_parent_data sdclk_mux[] = {<br>
> + { .fw_name = "sdclk-mux", .name = "sdclk-mux" }, };<br>
> +<br>
> +static const struct clk_parent_data huartxclk[] = {<br>
> + { .fw_name = "huartxclk", .name = "huartxclk" }, };<br>
> +<br>
> +static const struct clk_parent_data uxclk[] = {<br>
> + { .fw_name = "uxclk", .name = "uxclk" }, };<br>
> +<br>
> +static const struct clk_parent_data huxclk[] = {<br>
> + { .fw_name = "huxclk", .name = "huxclk" }, };<br>
> +<br>
> +static const struct clk_parent_data uart0clk[] = {<br>
> + { .fw_name = "uart0clk", .name = "uart0clk" }, };<br>
> +<br>
> +static const struct clk_parent_data uart1clk[] = {<br>
> + { .fw_name = "uart1clk", .name = "uart1clk" }, };<br>
> +<br>
> +static const struct clk_parent_data uart2clk[] = {<br>
> + { .fw_name = "uart2clk", .name = "uart2clk" }, };<br>
> +<br>
> +static const struct clk_parent_data uart3clk[] = {<br>
> + { .fw_name = "uart3clk", .name = "uart3clk" }, };<br>
> +<br>
> +static const struct clk_parent_data uart5clk[] = {<br>
> + { .fw_name = "uart5clk", .name = "uart5clk" }, };<br>
> +<br>
> +static const struct clk_parent_data uart4clk[] = {<br>
> + { .fw_name = "uart4clk", .name = "uart4clk" }, };<br>
> +<br>
> +static const struct clk_parent_data uart6clk[] = {<br>
> + { .fw_name = "uart6clk", .name = "uart6clk" }, };<br>
> +<br>
> +static const struct clk_parent_data uart7clk[] = {<br>
> + { .fw_name = "uart7clk", .name = "uart7clk" }, };<br>
> +<br>
> +static const struct clk_parent_data uart8clk[] = {<br>
> + { .fw_name = "uart8clk", .name = "uart8clk" }, };<br>
> +<br>
> +static const struct clk_parent_data uart9clk[] = {<br>
> + { .fw_name = "uart9clk", .name = "uart9clk" }, };<br>
> +<br>
> +static const struct clk_parent_data uart10clk[] = {<br>
> + { .fw_name = "uart10clk", .name = "uart10clk" }, };<br>
> +<br>
> +static const struct clk_parent_data uart11clk[] = {<br>
> + { .fw_name = "uart11clk", .name = "uart11clk" }, };<br>
> +<br>
> +static const struct clk_parent_data uart12clk[] = {<br>
> + { .fw_name = "uart12clk", .name = "uart12clk" }, };<br>
> +<br>
> +static const struct clk_parent_data uart13clk[] = {<br>
> + { .fw_name = "uart13clk", .name = "uart13clk" }, };<br>
> +<br>
> +static const struct clk_parent_data uart14clk[] = {<br>
> + { .fw_name = "uart14clk", .name = "uart14clk" }, };<br>
> +<br>
> +static const struct clk_parent_data soc1_i3c[] = {<br>
> + { .fw_name = "soc1-i3c", .name = "soc1-i3c" }, };<br>
> +<br>
> +static const struct clk_parent_data canclk[] = {<br>
> + { .fw_name = "canclk", .name = "canclk" }, };<br>
> +<br>
> +static const struct clk_parent_data rmii[] = {<br>
> + { .fw_name = "rmii", .name = "rmii" }, };<br>
> +<br>
> +static const struct clk_parent_data hclk_clk_sels[] = {<br>
> + { .fw_name = "soc0-hpll", .name = "soc0-hpll" },<br>
> + { .fw_name = "soc0-mpll", .name = "soc0-mpll" }, };<br>
> +<br>
> +static const struct clk_parent_data mhpll_clk_sels[] = {<br>
> + { .fw_name = "soc0-mpll", .name = "soc0-mpll" },<br>
> + { .fw_name = "soc0-hpll", .name = "soc0-hpll" }, };<br>
> +<br>
> +static const struct clk_parent_data mphy_clk_sels[] = {<br>
> + { .fw_name = "soc0-mpll", .name = "soc0-mpll" },<br>
> + { .fw_name = "soc0-hpll", .name = "soc0-hpll" },<br>
> + { .fw_name = "soc0-dpll", .name = "soc0-dpll" },<br>
> + { .fw_name = "soc0-clk192Mhz", .name = "soc0-clk192Mhz" }, };<br>
> +<br>
> +static const struct clk_parent_data psp_clk_sels[] = {<br>
> + { .fw_name = "soc0-mpll", .name = "soc0-mpll" },<br>
> + { .fw_name = "soc0-hpll", .name = "soc0-hpll" },<br>
> + { .fw_name = "soc0-hpll", .name = "soc0-hpll" },<br>
> + { .fw_name = "soc0-hpll", .name = "soc0-hpll" },<br>
> + { .fw_name = "soc0-mpll_div2", .name = "soc0-mpll_div2" },<br>
> + { .fw_name = "soc0-hpll_div2", .name = "soc0-hpll_div2" },<br>
> + { .fw_name = "soc0-hpll", .name = "soc0-hpll" },<br>
> + { .fw_name = "soc0-hpll", .name = "soc0-hpll" }, };<br>
> +<br>
> +static const struct clk_parent_data uart_clk_sels[] = {<br>
> + { .fw_name = "soc0-clk24Mhz", .name = "soc0-clk24Mhz" },<br>
> + { .fw_name = "soc0-clk192Mhz", .name = "soc0-clk192Mhz" }, };<br>
> +<br>
> +static const struct clk_parent_data emmc_clk_sels[] = {<br>
> + { .fw_name = "soc0-mpll_div4", .name = "soc0-mpll_div4" },<br>
> + { .fw_name = "soc0-hpll_div4", .name = "soc0-hpll_div4" }, };<br>
> +<br>
> +static const struct clk_parent_data sdio_clk_sels[] = {<br>
> + { .fw_name = "soc1-hpll", .name = "soc1-hpll" },<br>
> + { .fw_name = "soc1-apll", .name = "soc1-apll" }, };<br>
> +<br>
> +static const struct clk_parent_data ux_clk_sels[] = {<br>
> + { .fw_name = "soc1-apll_div4", .name = "soc1-apll_div4" },<br>
> + { .fw_name = "soc1-apll_div2", .name = "soc1-apll_div2" },<br>
> + { .fw_name = "soc1-apll", .name = "soc1-apll" },<br>
> + { .fw_name = "soc1-hpll", .name = "soc1-hpll" }, };<br>
> +<br>
> +static const struct clk_parent_data uartx_clk_sels[] = {<br>
> + { .fw_name = "uartxclk", .name = "uartxclk" },<br>
> + { .fw_name = "huartxclk", .name = "huartxclk" }, };<br>
> +<br>
> +#define FIXED_CLK(_id, _name, _rate) \<br>
> + [_id] = { \<br>
> + .type = CLK_FIXED, \<br>
> + .name = _name, \<br>
> + .data = { .rate = { .fixed_rate = _rate, } }, \<br>
> + }<br>
> +<br>
> +#define PLL_CLK(_id, _type, _name, _parent, _reg) \<br>
> + [_id] = { \<br>
> + .type = _type, \<br>
> + .name = _name, \<br>
> + .data = { .pll = { .parent = _parent, .reg = _reg, } }, \<br>
> + }<br>
> +<br>
> +#define MUX_CLK(_id, _name, _parents, _num_parents, _reg, _shift, _width)<br>
> \<br>
> + [_id] = { \<br>
> + .type = CLK_MUX, \<br>
> + .name = _name, \<br>
> + .data = { \<br>
> + .mux = { \<br>
> + .parents = _parents, \<br>
> + .num_parents = _num_parents, \<br>
> + .reg = _reg, \<br>
> + .bit_shift = _shift, \<br>
> + .bit_width = _width, \<br>
> + }, \<br>
> + }, \<br>
> + }<br>
> +<br>
> +#define DIVIDER_CLK(_id, _name, _parent, _reg, _shift, _width, _div_table) \<br>
> + [_id] = { \<br>
> + .type = CLK_DIVIDER, \<br>
> + .name = _name, \<br>
> + .data = { \<br>
> + .div = { \<br>
> + .parent = _parent, \<br>
> + .reg = _reg, \<br>
> + .bit_shift = _shift, \<br>
> + .bit_width = _width, \<br>
> + .div_table = _div_table, \<br>
> + }, \<br>
> + }, \<br>
> + }<br>
> +<br>
> +#define FIXED_FACTOR_CLK(_id, _name, _parent, _mult, _div) \<br>
> + [_id] = { \<br>
> + .type = CLK_FIXED_FACTOR, \<br>
> + .name = _name, \<br>
> + .data = { .factor = { .parent = _parent, .mult = _mult, .div = _div, } }, \<br>
> + }<br>
> +<br>
> +#define GATE_CLK(_id, _type, _name, _parent, _reg, _bit, _flags) \<br>
> + [_id] = { \<br>
> + .type = _type, \<br>
> + .name = _name, \<br>
> + .data = { \<br>
> + .gate = { \<br>
> + .parent = _parent, \<br>
> + .reg = _reg, \<br>
> + .bit = _bit, \<br>
> + .flags = _flags, \<br>
> + }, \<br>
> + }, \<br>
> + }<br>
> +<br>
> +static const struct ast2700_clk_info ast2700_scu0_clk_info[] __initconst = {<br>
> + FIXED_CLK(SCU0_CLKIN, "soc0-clkin", SCU_CLK_25MHZ),<br>
> + FIXED_CLK(SCU0_CLK_24M, "soc0-clk24Mhz", SCU_CLK_24MHZ),<br>
> + FIXED_CLK(SCU0_CLK_192M, "soc0-clk192Mhz", SCU_CLK_192MHZ),<br>
> + FIXED_CLK(SCU0_CLK_U2PHY_CLK12M, "u2phy_clk12m",<br>
> SCU_CLK_12MHZ),<br>
> + PLL_CLK(SCU0_CLK_HPLL, CLK_HPLL, "soc0-hpll", soc0_clkin,<br>
> SCU0_HPLL_PARAM),<br>
> + PLL_CLK(SCU0_CLK_DPLL, CLK_PLL, "soc0-dpll", soc0_clkin,<br>
> SCU0_DPLL_PARAM),<br>
> + PLL_CLK(SCU0_CLK_MPLL, CLK_PLL, "soc0-mpll", soc0_clkin,<br>
> SCU0_MPLL_PARAM),<br>
> + PLL_CLK(SCU0_CLK_D0, DCLK_FIXED, "d0clk", NULL,<br>
> SCU0_D0CLK_PARAM),<br>
> + PLL_CLK(SCU0_CLK_D1, DCLK_FIXED, "d1clk", NULL,<br>
> SCU0_D1CLK_PARAM),<br>
> + PLL_CLK(SCU0_CLK_CRT0, DCLK_FIXED, "crt0clk", NULL,<br>
> SCU0_CRT0CLK_PARAM),<br>
> + PLL_CLK(SCU0_CLK_CRT1, DCLK_FIXED, "crt1clk", NULL,<br>
> SCU0_CRT1CLK_PARAM),<br>
> + PLL_CLK(SCU0_CLK_MPHY, CLK_MISC, "mphyclk", mphysrc,<br>
> SCU0_MPHYCLK_PARAM),<br>
> + PLL_CLK(SCU0_CLK_U2PHY_REFCLK, CLK_MISC, "u2phy_refclk",<br>
> u2phy_refclksrc, SCU0_CLK_SEL2),<br>
> + FIXED_FACTOR_CLK(SCU0_CLK_HPLL_DIV2, "soc0-hpll_div2", soc0_hpll, 1,<br>
> 2),<br>
> + FIXED_FACTOR_CLK(SCU0_CLK_HPLL_DIV4, "soc0-hpll_div4", soc0_hpll, 1,<br>
> 4),<br>
> + FIXED_FACTOR_CLK(SCU0_CLK_MPLL_DIV2, "soc0-mpll_div2", soc0_mpll,<br>
> 1, 2),<br>
> + FIXED_FACTOR_CLK(SCU0_CLK_MPLL_DIV4, "soc0-mpll_div4", soc0_mpll,<br>
> 1, 4),<br>
> + FIXED_FACTOR_CLK(SCU0_CLK_MPLL_DIV8, "soc0-mpll_div8", soc0_mpll,<br>
> 1, 8),<br>
> + FIXED_FACTOR_CLK(SCU0_CLK_AXI0, "axi0clk", pspclk, 1, 2),<br>
> + FIXED_FACTOR_CLK(SCU0_CLK_AXI1, "axi1clk", soc0_mpll, 1, 4),<br>
> + DIVIDER_CLK(SCU0_CLK_AHB, "soc0-ahb", soc0_ahbmux,<br>
> + SCU0_HWSTRAP1, 5, 2, ast2700_hclk_div_table),<br>
> + DIVIDER_CLK(SCU0_CLK_EMMC, "emmcclk", emmcsrc_mux,<br>
> + SCU0_CLK_SEL1, 12, 3, ast2700_clk_div_table2),<br>
> + DIVIDER_CLK(SCU0_CLK_APB, "soc0-apb", axi0clk,<br>
> + SCU0_CLK_SEL1, 23, 3, ast2700_clk_div_table2),<br>
> + DIVIDER_CLK(SCU0_CLK_UART4, "uart4clk", soc0_uartclk,<br>
> + SCU0_CLK_SEL2, 30, 1, ast2700_clk_uart_div_table),<br>
> + DIVIDER_CLK(SCU0_CLK_HPLL_DIV_AHB, "soc0-hpll-ahb", soc0_hpll,<br>
> + SCU0_HWSTRAP1, 5, 2, ast2700_hclk_div_table),<br>
> + DIVIDER_CLK(SCU0_CLK_MPLL_DIV_AHB, "soc0-mpll-ahb", soc0_mpll,<br>
> + SCU0_HWSTRAP1, 5, 2, ast2700_hclk_div_table),<br>
> + MUX_CLK(SCU0_CLK_PSP, "pspclk", psp_clk_sels,<br>
> ARRAY_SIZE(psp_clk_sels),<br>
> + SCU0_HWSTRAP1, 2, 3),<br>
> + MUX_CLK(SCU0_CLK_AHBMUX, "soc0-ahbmux", hclk_clk_sels,<br>
> ARRAY_SIZE(hclk_clk_sels),<br>
> + SCU0_HWSTRAP1, 7, 1),<br>
> + MUX_CLK(SCU0_CLK_EMMCMUX, "emmcsrc-mux", emmc_clk_sels,<br>
> ARRAY_SIZE(emmc_clk_sels),<br>
> + SCU0_CLK_SEL1, 11, 1),<br>
> + MUX_CLK(SCU0_CLK_MPHYSRC, "mphysrc", mphy_clk_sels,<br>
> ARRAY_SIZE(mphy_clk_sels),<br>
> + SCU0_CLK_SEL2, 18, 2),<br>
> + MUX_CLK(SCU0_CLK_U2PHY_REFCLKSRC, "u2phy_refclksrc",<br>
> mhpll_clk_sels,<br>
> + ARRAY_SIZE(mhpll_clk_sels), SCU0_CLK_SEL2, 23, 1),<br>
> + MUX_CLK(SCU0_CLK_UART, "soc0-uartclk", uart_clk_sels,<br>
> ARRAY_SIZE(uart_clk_sels),<br>
> + SCU0_CLK_SEL2, 14, 1),<br>
> + GATE_CLK(SCU0_CLK_GATE_MCLK, CLK_GATE_ASPEED, "mclk-gate",<br>
> soc0_mpll,<br>
> + SCU0_CLK_STOP, 0, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU0_CLK_GATE_ECLK, CLK_GATE_ASPEED, "eclk-gate", NULL,<br>
> SCU0_CLK_STOP, 1, 0),<br>
> + GATE_CLK(SCU0_CLK_GATE_2DCLK, CLK_GATE_ASPEED, "gclk-gate", NULL,<br>
> SCU0_CLK_STOP, 2, 0),<br>
> + GATE_CLK(SCU0_CLK_GATE_VCLK, CLK_GATE_ASPEED, "vclk-gate", NULL,<br>
> SCU0_CLK_STOP, 3, 0),<br>
> + GATE_CLK(SCU0_CLK_GATE_BCLK, CLK_GATE_ASPEED, "bclk-gate", NULL,<br>
> + SCU0_CLK_STOP, 4, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU0_CLK_GATE_VGA0CLK, CLK_GATE_ASPEED,<br>
> "vga0clk-gate", NULL,<br>
> + SCU0_CLK_STOP, 5, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU0_CLK_GATE_REFCLK, CLK_GATE_ASPEED,<br>
> "soc0-refclk-gate", soc0_clkin,<br>
> + SCU0_CLK_STOP, 6, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU0_CLK_GATE_PORTBUSB2CLK, CLK_GATE_ASPEED,<br>
> "portb-usb2clk-gate", NULL,<br>
> + SCU0_CLK_STOP, 7, 0),<br>
> + GATE_CLK(SCU0_CLK_GATE_UHCICLK, CLK_GATE_ASPEED, "uhciclk-gate",<br>
> NULL, SCU0_CLK_STOP, 9, 0),<br>
> + GATE_CLK(SCU0_CLK_GATE_VGA1CLK, CLK_GATE_ASPEED, "vga1clk-gate",<br>
> NULL,<br>
> + SCU0_CLK_STOP, 10, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU0_CLK_GATE_DDRPHYCLK, CLK_GATE_ASPEED,<br>
> "ddrphy-gate", NULL,<br>
> + SCU0_CLK_STOP, 11, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU0_CLK_GATE_E2M0CLK, CLK_GATE_ASPEED,<br>
> "e2m0clk-gate", NULL,<br>
> + SCU0_CLK_STOP, 12, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU0_CLK_GATE_HACCLK, CLK_GATE_ASPEED, "hacclk-gate",<br>
> NULL, SCU0_CLK_STOP, 13, 0),<br>
> + GATE_CLK(SCU0_CLK_GATE_PORTAUSB2CLK, CLK_GATE_ASPEED,<br>
> "porta-usb2clk-gate", NULL,<br>
> + SCU0_CLK_STOP, 14, 0),<br>
> + GATE_CLK(SCU0_CLK_GATE_UART4CLK, CLK_GATE_ASPEED,<br>
> "uart4clk-gate", uart4clk,<br>
> + SCU0_CLK_STOP, 15, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU0_CLK_GATE_SLICLK, CLK_GATE_ASPEED, "soc0-sliclk-gate",<br>
> NULL,<br>
> + SCU0_CLK_STOP, 16, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU0_CLK_GATE_DACCLK, CLK_GATE_ASPEED, "dacclk-gate",<br>
> NULL,<br>
> + SCU0_CLK_STOP, 17, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU0_CLK_GATE_DP, CLK_GATE_ASPEED, "dpclk-gate", NULL,<br>
> + SCU0_CLK_STOP, 18, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU0_CLK_GATE_E2M1CLK, CLK_GATE_ASPEED,<br>
> "e2m1clk-gate", NULL,<br>
> + SCU0_CLK_STOP, 19, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU0_CLK_GATE_CRT0CLK, CLK_GATE_ASPEED, "crt0clk-gate",<br>
> NULL,<br>
> + SCU0_CLK_STOP, 20, 0),<br>
> + GATE_CLK(SCU0_CLK_GATE_CRT1CLK, CLK_GATE_ASPEED, "crt1clk-gate",<br>
> NULL,<br>
> + SCU0_CLK_STOP, 21, 0),<br>
> + GATE_CLK(SCU0_CLK_GATE_ECDSACLK, CLK_GATE_ASPEED, "eccclk-gate",<br>
> NULL,<br>
> + SCU0_CLK_STOP, 23, 0),<br>
> + GATE_CLK(SCU0_CLK_GATE_RSACLK, CLK_GATE_ASPEED, "rsaclk-gate",<br>
> NULL,<br>
> + SCU0_CLK_STOP, 24, 0),<br>
> + GATE_CLK(SCU0_CLK_GATE_RVAS0CLK, CLK_GATE_ASPEED,<br>
> "rvas0clk-gate", NULL,<br>
> + SCU0_CLK_STOP, 25, 0),<br>
> + GATE_CLK(SCU0_CLK_GATE_UFSCLK, CLK_GATE_ASPEED, "ufsclk-gate",<br>
> NULL,<br>
> + SCU0_CLK_STOP, 26, 0),<br>
> + GATE_CLK(SCU0_CLK_GATE_EMMCCLK, CLK_GATE_ASPEED,<br>
> "emmcclk-gate", emmcclk,<br>
> + SCU0_CLK_STOP, 27, 0),<br>
> + GATE_CLK(SCU0_CLK_GATE_RVAS1CLK, CLK_GATE_ASPEED,<br>
> "rvas1clk-gate", NULL,<br>
> + SCU0_CLK_STOP, 28, 0),<br>
> +};<br>
> +<br>
> +static const struct ast2700_clk_info ast2700_scu1_clk_info[] __initconst = {<br>
> + FIXED_CLK(SCU1_CLKIN, "soc1-clkin", SCU_CLK_25MHZ),<br>
> + PLL_CLK(SCU1_CLK_HPLL, CLK_PLL, "soc1-hpll", soc1_clkin,<br>
> SCU1_HPLL_PARAM),<br>
> + PLL_CLK(SCU1_CLK_APLL, CLK_PLL, "soc1-apll", soc1_clkin,<br>
> SCU1_APLL_PARAM),<br>
> + PLL_CLK(SCU1_CLK_DPLL, CLK_PLL, "soc1-dpll", soc1_clkin,<br>
> SCU1_DPLL_PARAM),<br>
> + PLL_CLK(SCU1_CLK_UARTX, CLK_UART_PLL, "uartxclk", uxclk,<br>
> SCU1_UXCLK_CTRL),<br>
> + PLL_CLK(SCU1_CLK_HUARTX, CLK_UART_PLL, "huartxclk", huxclk,<br>
> SCU1_HUXCLK_CTRL),<br>
> + FIXED_FACTOR_CLK(SCU1_CLK_APLL_DIV2, "soc1-apll_div2", soc1_apll, 1,<br>
> 2),<br>
> + FIXED_FACTOR_CLK(SCU1_CLK_APLL_DIV4, "soc1-apll_div4", soc1_apll, 1,<br>
> 4),<br>
> + FIXED_FACTOR_CLK(SCU1_CLK_UART13, "uart13clk", huartxclk, 1, 1),<br>
> + FIXED_FACTOR_CLK(SCU1_CLK_UART14, "uart14clk", huartxclk, 1, 1),<br>
> + FIXED_FACTOR_CLK(SCU1_CLK_CAN, "canclk", soc1_apll, 1, 10),<br>
> + DIVIDER_CLK(SCU1_CLK_SDCLK, "sdclk", sdclk_mux,<br>
> + SCU1_CLK_SEL1, 14, 3, ast2700_clk_div_table),<br>
> + DIVIDER_CLK(SCU1_CLK_APB, "soc1-apb", soc1_hpll,<br>
> + SCU1_CLK_SEL1, 18, 3, ast2700_clk_div_table2),<br>
> + DIVIDER_CLK(SCU1_CLK_RMII, "rmii", soc1_hpll,<br>
> + SCU1_CLK_SEL1, 21, 3, ast2700_rmii_div_table),<br>
> + DIVIDER_CLK(SCU1_CLK_RGMII, "rgmii", soc1_hpll,<br>
> + SCU1_CLK_SEL1, 25, 3, ast2700_rgmii_div_table),<br>
> + DIVIDER_CLK(SCU1_CLK_MACHCLK, "machclk", soc1_hpll,<br>
> + SCU1_CLK_SEL1, 29, 3, ast2700_clk_div_table),<br>
> + DIVIDER_CLK(SCU1_CLK_APLL_DIVN, "soc1-apll_divn", soc1_apll,<br>
> + SCU1_CLK_SEL2, 8, 3, ast2700_clk_div_table),<br>
> + DIVIDER_CLK(SCU1_CLK_AHB, "soc1-ahb", soc1_hpll,<br>
> + SCU1_CLK_SEL2, 20, 3, ast2700_clk_div_table),<br>
> + DIVIDER_CLK(SCU1_CLK_I3C, "soc1-i3c", soc1_hpll,<br>
> + SCU1_CLK_SEL2, 23, 3, ast2700_clk_div_table),<br>
> + MUX_CLK(SCU1_CLK_UART0, "uart0clk", uartx_clk_sels,<br>
> ARRAY_SIZE(uartx_clk_sels),<br>
> + SCU1_CLK_SEL1, 0, 1),<br>
> + MUX_CLK(SCU1_CLK_UART1, "uart1clk", uartx_clk_sels,<br>
> ARRAY_SIZE(uartx_clk_sels),<br>
> + SCU1_CLK_SEL1, 1, 1),<br>
> + MUX_CLK(SCU1_CLK_UART2, "uart2clk", uartx_clk_sels,<br>
> ARRAY_SIZE(uartx_clk_sels),<br>
> + SCU1_CLK_SEL1, 2, 1),<br>
> + MUX_CLK(SCU1_CLK_UART3, "uart3clk", uartx_clk_sels,<br>
> ARRAY_SIZE(uartx_clk_sels),<br>
> + SCU1_CLK_SEL1, 3, 1),<br>
> + MUX_CLK(SCU1_CLK_UART5, "uart5clk", uartx_clk_sels,<br>
> ARRAY_SIZE(uartx_clk_sels),<br>
> + SCU1_CLK_SEL1, 5, 1),<br>
> + MUX_CLK(SCU1_CLK_UART6, "uart6clk", uartx_clk_sels,<br>
> ARRAY_SIZE(uartx_clk_sels),<br>
> + SCU1_CLK_SEL1, 6, 1),<br>
> + MUX_CLK(SCU1_CLK_UART7, "uart7clk", uartx_clk_sels,<br>
> ARRAY_SIZE(uartx_clk_sels),<br>
> + SCU1_CLK_SEL1, 7, 1),<br>
> + MUX_CLK(SCU1_CLK_UART8, "uart8clk", uartx_clk_sels,<br>
> ARRAY_SIZE(uartx_clk_sels),<br>
> + SCU1_CLK_SEL1, 8, 1),<br>
> + MUX_CLK(SCU1_CLK_UART9, "uart9clk", uartx_clk_sels,<br>
> ARRAY_SIZE(uartx_clk_sels),<br>
> + SCU1_CLK_SEL1, 9, 1),<br>
> + MUX_CLK(SCU1_CLK_UART10, "uart10clk", uartx_clk_sels,<br>
> ARRAY_SIZE(uartx_clk_sels),<br>
> + SCU1_CLK_SEL1, 10, 1),<br>
> + MUX_CLK(SCU1_CLK_UART11, "uart11clk", uartx_clk_sels,<br>
> ARRAY_SIZE(uartx_clk_sels),<br>
> + SCU1_CLK_SEL1, 11, 1),<br>
> + MUX_CLK(SCU1_CLK_UART12, "uart12clk", uartx_clk_sels,<br>
> ARRAY_SIZE(uartx_clk_sels),<br>
> + SCU1_CLK_SEL1, 12, 1),<br>
> + MUX_CLK(SCU1_CLK_SDMUX, "sdclk-mux", sdio_clk_sels,<br>
> ARRAY_SIZE(sdio_clk_sels),<br>
> + SCU1_CLK_SEL1, 13, 1),<br>
> + MUX_CLK(SCU1_CLK_UXCLK, "uxclk", ux_clk_sels,<br>
> ARRAY_SIZE(ux_clk_sels),<br>
> + SCU1_CLK_SEL2, 0, 2),<br>
> + MUX_CLK(SCU1_CLK_HUXCLK, "huxclk", ux_clk_sels,<br>
> ARRAY_SIZE(ux_clk_sels),<br>
> + SCU1_CLK_SEL2, 3, 2),<br>
> + GATE_CLK(SCU1_CLK_MAC0RCLK, CLK_GATE, "mac0rclk-gate", rmii,<br>
> SCU1_MAC12_CLK_DLY, 29, 0),<br>
> + GATE_CLK(SCU1_CLK_MAC1RCLK, CLK_GATE, "mac1rclk-gate", rmii,<br>
> SCU1_MAC12_CLK_DLY, 30, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_LCLK0, CLK_GATE_ASPEED, "lclk0-gate",<br>
> NULL,<br>
> + SCU1_CLK_STOP, 0, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_LCLK1, CLK_GATE_ASPEED, "lclk1-gate",<br>
> NULL,<br>
> + SCU1_CLK_STOP, 1, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_ESPI0CLK, CLK_GATE_ASPEED,<br>
> "espi0clk-gate", NULL,<br>
> + SCU1_CLK_STOP, 2, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_ESPI1CLK, CLK_GATE_ASPEED,<br>
> "espi1clk-gate", NULL,<br>
> + SCU1_CLK_STOP, 3, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_SDCLK, CLK_GATE_ASPEED, "sdclk-gate",<br>
> sdclk,<br>
> + SCU1_CLK_STOP, 4, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_IPEREFCLK, CLK_GATE_ASPEED,<br>
> "soc1-iperefclk-gate", NULL,<br>
> + SCU1_CLK_STOP, 5, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_REFCLK, CLK_GATE_ASPEED,<br>
> "soc1-refclk-gate", NULL,<br>
> + SCU1_CLK_STOP, 6, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_LPCHCLK, CLK_GATE_ASPEED, "lpchclk-gate",<br>
> NULL,<br>
> + SCU1_CLK_STOP, 7, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_MAC0CLK, CLK_GATE_ASPEED,<br>
> "mac0clk-gate", NULL,<br>
> + SCU1_CLK_STOP, 8, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_MAC1CLK, CLK_GATE_ASPEED,<br>
> "mac1clk-gate", NULL,<br>
> + SCU1_CLK_STOP, 9, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_MAC2CLK, CLK_GATE_ASPEED,<br>
> "mac2clk-gate", NULL,<br>
> + SCU1_CLK_STOP, 10, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_UART0CLK, CLK_GATE_ASPEED,<br>
> "uart0clk-gate", uart0clk,<br>
> + SCU1_CLK_STOP, 11, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_UART1CLK, CLK_GATE_ASPEED,<br>
> "uart1clk-gate", uart1clk,<br>
> + SCU1_CLK_STOP, 12, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_UART2CLK, CLK_GATE_ASPEED,<br>
> "uart2clk-gate", uart2clk,<br>
> + SCU1_CLK_STOP, 13, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_UART3CLK, CLK_GATE_ASPEED,<br>
> "uart3clk-gate", uart3clk,<br>
> + SCU1_CLK_STOP, 14, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_I2CCLK, CLK_GATE_ASPEED, "i2cclk-gate",<br>
> NULL, SCU1_CLK_STOP, 15, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_I3C0CLK, CLK_GATE_ASPEED, "i3c0clk-gate",<br>
> soc1_i3c,<br>
> + SCU1_CLK_STOP, 16, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_I3C1CLK, CLK_GATE_ASPEED, "i3c1clk-gate",<br>
> soc1_i3c,<br>
> + SCU1_CLK_STOP, 17, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_I3C2CLK, CLK_GATE_ASPEED, "i3c2clk-gate",<br>
> soc1_i3c,<br>
> + SCU1_CLK_STOP, 18, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_I3C3CLK, CLK_GATE_ASPEED, "i3c3clk-gate",<br>
> soc1_i3c,<br>
> + SCU1_CLK_STOP, 19, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_I3C4CLK, CLK_GATE_ASPEED, "i3c4clk-gate",<br>
> soc1_i3c,<br>
> + SCU1_CLK_STOP, 20, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_I3C5CLK, CLK_GATE_ASPEED, "i3c5clk-gate",<br>
> soc1_i3c,<br>
> + SCU1_CLK_STOP, 21, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_I3C6CLK, CLK_GATE_ASPEED, "i3c6clk-gate",<br>
> soc1_i3c,<br>
> + SCU1_CLK_STOP, 22, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_I3C7CLK, CLK_GATE_ASPEED, "i3c7clk-gate",<br>
> soc1_i3c,<br>
> + SCU1_CLK_STOP, 23, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_I3C8CLK, CLK_GATE_ASPEED, "i3c8clk-gate",<br>
> soc1_i3c,<br>
> + SCU1_CLK_STOP, 24, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_I3C9CLK, CLK_GATE_ASPEED, "i3c9clk-gate",<br>
> soc1_i3c,<br>
> + SCU1_CLK_STOP, 25, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_I3C10CLK, CLK_GATE_ASPEED,<br>
> "i3c10clk-gate", soc1_i3c,<br>
> + SCU1_CLK_STOP, 26, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_I3C11CLK, CLK_GATE_ASPEED,<br>
> "i3c11clk-gate", soc1_i3c,<br>
> + SCU1_CLK_STOP, 27, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_I3C12CLK, CLK_GATE_ASPEED,<br>
> "i3c12clk-gate", soc1_i3c,<br>
> + SCU1_CLK_STOP, 28, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_I3C13CLK, CLK_GATE_ASPEED,<br>
> "i3c13clk-gate", soc1_i3c,<br>
> + SCU1_CLK_STOP, 29, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_I3C14CLK, CLK_GATE_ASPEED,<br>
> "i3c14clk-gate", soc1_i3c,<br>
> + SCU1_CLK_STOP, 30, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_I3C15CLK, CLK_GATE_ASPEED,<br>
> "i3c15clk-gate", soc1_i3c,<br>
> + SCU1_CLK_STOP, 31, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_UART5CLK, CLK_GATE_ASPEED,<br>
> "uart5clk-gate", uart5clk,<br>
> + SCU1_CLK_STOP2, 0, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_UART6CLK, CLK_GATE_ASPEED,<br>
> "uart6clk-gate", uart6clk,<br>
> + SCU1_CLK_STOP2, 1, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_UART7CLK, CLK_GATE_ASPEED,<br>
> "uart7clk-gate", uart7clk,<br>
> + SCU1_CLK_STOP2, 2, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_UART8CLK, CLK_GATE_ASPEED,<br>
> "uart8clk-gate", uart8clk,<br>
> + SCU1_CLK_STOP2, 3, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_UART9CLK, CLK_GATE_ASPEED,<br>
> "uart9clk-gate", uart9clk,<br>
> + SCU1_CLK_STOP2, 4, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_UART10CLK, CLK_GATE_ASPEED,<br>
> "uart10clk-gate", uart10clk,<br>
> + SCU1_CLK_STOP2, 5, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_UART11CLK, CLK_GATE_ASPEED,<br>
> "uart11clk-gate", uart11clk,<br>
> + SCU1_CLK_STOP2, 6, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_UART12CLK, CLK_GATE_ASPEED,<br>
> "uart12clk-gate", uart12clk,<br>
> + SCU1_CLK_STOP2, 7, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_FSICLK, CLK_GATE_ASPEED, "fsiclk-gate",<br>
> NULL, SCU1_CLK_STOP2, 8, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_LTPIPHYCLK, CLK_GATE_ASPEED,<br>
> "ltpiphyclk-gate", NULL,<br>
> + SCU1_CLK_STOP2, 9, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_LTPICLK, CLK_GATE_ASPEED, "ltpiclk-gate",<br>
> NULL,<br>
> + SCU1_CLK_STOP2, 10, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_VGALCLK, CLK_GATE_ASPEED, "vgalclk-gate",<br>
> NULL,<br>
> + SCU1_CLK_STOP2, 11, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_UHCICLK, CLK_GATE_ASPEED,<br>
> "usbuartclk-gate", NULL,<br>
> + SCU1_CLK_STOP2, 12, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_CANCLK, CLK_GATE_ASPEED, "canclk-gate",<br>
> canclk,<br>
> + SCU1_CLK_STOP2, 13, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_PCICLK, CLK_GATE_ASPEED, "pciclk-gate",<br>
> NULL,<br>
> + SCU1_CLK_STOP2, 14, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_SLICLK, CLK_GATE_ASPEED, "soc1-sliclk-gate",<br>
> NULL,<br>
> + SCU1_CLK_STOP2, 15, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_E2MCLK, CLK_GATE_ASPEED,<br>
> "soc1-e2m-gate", NULL,<br>
> + SCU1_CLK_STOP2, 16, CLK_IS_CRITICAL),<br>
> + GATE_CLK(SCU1_CLK_GATE_PORTCUSB2CLK, CLK_GATE_ASPEED,<br>
> "portcusb2-gate", NULL,<br>
> + SCU1_CLK_STOP2, 17, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_PORTDUSB2CLK, CLK_GATE_ASPEED,<br>
> "portdusb2-gate", NULL,<br>
> + SCU1_CLK_STOP2, 18, 0),<br>
> + GATE_CLK(SCU1_CLK_GATE_LTPI1TXCLK, CLK_GATE_ASPEED,<br>
> "ltp1tx-gate", NULL,<br>
> + SCU1_CLK_STOP2, 19, 0),<br>
> +};<br>
> +<br>
> +static struct clk_hw *ast2700_clk_hw_register_hpll(void __iomem *reg,<br>
> + const char *name, const char *parent_name,<br>
> + struct ast2700_clk_ctrl *clk_ctrl) {<br>
> + unsigned int mult, div;<br>
> + u32 val;<br>
> +<br>
> + val = readl(clk_ctrl->base + SCU0_HWSTRAP1);<br>
> + if ((readl(clk_ctrl->base) & REVISION_ID) && (val & BIT(3))) {<br>
> + switch ((val & GENMASK(4, 2)) >> 2) {<br>
> + case 2:<br>
> + return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name,<br>
> NULL,<br>
> + 0, 1800 * HZ_PER_MHZ);<br>
> + case 3:<br>
> + return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name,<br>
> NULL,<br>
> + 0, 1700 * HZ_PER_MHZ);<br>
> + case 6:<br>
> + return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name,<br>
> NULL,<br>
> + 0, 1200 * HZ_PER_MHZ);<br>
> + case 7:<br>
> + return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name,<br>
> NULL,<br>
> + 0, 800 * HZ_PER_MHZ);<br>
> + default:<br>
> + return ERR_PTR(-EINVAL);<br>
> + }<br>
> + } else if ((val & GENMASK(3, 2)) != 0) {<br>
> + switch ((val & GENMASK(3, 2)) >> 2) {<br>
> + case 1:<br>
> + return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name,<br>
> NULL,<br>
> + 0, 1900 * HZ_PER_MHZ);<br>
> + case 2:<br>
> + return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name,<br>
> NULL,<br>
> + 0, 1800 * HZ_PER_MHZ);<br>
> + case 3:<br>
> + return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name,<br>
> NULL,<br>
> + 0, 1700 * HZ_PER_MHZ);<br>
> + default:<br>
> + return ERR_PTR(-EINVAL);<br>
> + }<br>
> + } else {<br>
> + val = readl(reg);<br>
> +<br>
> + if (val & BIT(24)) {<br>
> + /* Pass through mode */<br>
> + mult = 1;<br>
> + div = 1;<br>
> + } else {<br>
> + u32 m = val & 0x1fff;<br>
> + u32 n = (val >> 13) & 0x3f;<br>
> + u32 p = (val >> 19) & 0xf;<br>
> +<br>
> + mult = (m + 1) / (2 * (n + 1));<br>
> + div = (p + 1);<br>
> + }<br>
> + }<br>
> +<br>
> + return devm_clk_hw_register_fixed_factor(clk_ctrl->dev, name,<br>
> +parent_name, 0, mult, div); }<br>
> +<br>
> +static struct clk_hw *ast2700_clk_hw_register_pll(int clk_idx, void __iomem<br>
> *reg,<br>
> + const char *name, const char *parent_name,<br>
> + struct ast2700_clk_ctrl *clk_ctrl) {<br>
> + int scu = clk_ctrl->clk_data->scu;<br>
> + unsigned int mult, div;<br>
> + u32 val = readl(reg);<br>
> +<br>
> + if (val & BIT(24)) {<br>
> + /* Pass through mode */<br>
> + mult = 1;<br>
> + div = 1;<br>
> + } else {<br>
> + u32 m = val & 0x1fff;<br>
> + u32 n = (val >> 13) & 0x3f;<br>
> + u32 p = (val >> 19) & 0xf;<br>
> +<br>
> + if (scu) {<br>
> + mult = (m + 1) / (n + 1);<br>
> + div = (p + 1);<br>
> + } else {<br>
> + if (clk_idx == SCU0_CLK_MPLL) {<br>
> + mult = m / (n + 1);<br>
> + div = (p + 1);<br>
> + } else {<br>
> + mult = (m + 1) / (2 * (n + 1));<br>
> + div = (p + 1);<br>
> + }<br>
> + }<br>
> + }<br>
> +<br>
> + return devm_clk_hw_register_fixed_factor(clk_ctrl->dev, name,<br>
> +parent_name, 0, mult, div); }<br>
> +<br>
> +static struct clk_hw *ast2700_clk_hw_register_dclk(void __iomem *reg,<br>
> const char *name,<br>
> + struct ast2700_clk_ctrl *clk_ctrl) {<br>
> + unsigned int mult, div, r, n;<br>
> + u32 xdclk;<br>
> + u32 val;<br>
> +<br>
> + val = readl(clk_ctrl->base + 0x284);<br>
> + if (val & BIT(29))<br>
> + xdclk = 800 * HZ_PER_MHZ;<br>
> + else<br>
> + xdclk = 1000 * HZ_PER_MHZ;<br>
> +<br>
> + val = readl(reg);<br>
> + r = val & GENMASK(15, 0);<br>
> + n = (val >> 16) & GENMASK(15, 0);<br>
> + mult = r;<br>
> + div = 2 * n;<br>
> +<br>
> + return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, 0,<br>
> +(xdclk * mult) / div); }<br>
> +<br>
> +static struct clk_hw *ast2700_clk_hw_register_uartpll(void __iomem *reg,<br>
> + const char *name, const char<br>
> *parent_name,<br>
> + struct ast2700_clk_ctrl *clk_ctrl) {<br>
> + unsigned int mult, div;<br>
> + u32 val = readl(reg);<br>
> + u32 r = val & 0xff;<br>
> + u32 n = (val >> 8) & 0x3ff;<br>
> +<br>
> + mult = r;<br>
> + div = n * 2;<br>
> +<br>
> + return devm_clk_hw_register_fixed_factor(clk_ctrl->dev, name,<br>
> + parent_name, 0, mult, div);<br>
> +}<br>
> +<br>
> +static struct clk_hw *ast2700_clk_hw_register_misc(int clk_idx, void<br>
> __iomem *reg,<br>
> + const char *name, const char *parent_name,<br>
> + struct ast2700_clk_ctrl *clk_ctrl) {<br>
> + u32 div = 0;<br>
> +<br>
> + if (clk_idx == SCU0_CLK_MPHY) {<br>
> + div = readl(reg) + 1;<br>
> + } else if (clk_idx == SCU0_CLK_U2PHY_REFCLK) {<br>
> + if (readl(clk_ctrl->base) & REVISION_ID)<br>
> + div = (GET_USB_REFCLK_DIV(readl(reg)) + 1) << 4;<br>
> + else<br>
> + div = (GET_USB_REFCLK_DIV(readl(reg)) + 1) << 1;<br>
> + } else {<br>
> + return ERR_PTR(-EINVAL);<br>
> + }<br>
> +<br>
> + return devm_clk_hw_register_fixed_factor(clk_ctrl->dev, name,<br>
> + parent_name, 0, 1, div);<br>
> +}<br>
> +<br>
> +static int ast2700_clk_is_enabled(struct clk_hw *hw) {<br>
> + struct clk_gate *gate = to_clk_gate(hw);<br>
> + u32 clk = BIT(gate->bit_idx);<br>
> + u32 reg;<br>
> +<br>
> + reg = readl(gate->reg);<br>
> +<br>
> + return !(reg & clk);<br>
> +}<br>
> +<br>
> +static int ast2700_clk_enable(struct clk_hw *hw) {<br>
> + struct clk_gate *gate = to_clk_gate(hw);<br>
> + u32 clk = BIT(gate->bit_idx);<br>
> +<br>
> + if (readl(gate->reg) & clk)<br>
> + writel(clk, gate->reg + 0x04);<br>
> +<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static void ast2700_clk_disable(struct clk_hw *hw) {<br>
> + struct clk_gate *gate = to_clk_gate(hw);<br>
> + u32 clk = BIT(gate->bit_idx);<br>
> +<br>
> + /* Clock is set to enable, so use write to set register */<br>
> + writel(clk, gate->reg);<br>
> +}<br>
> +<br>
> +static const struct clk_ops ast2700_clk_gate_ops = {<br>
> + .enable = ast2700_clk_enable,<br>
> + .disable = ast2700_clk_disable,<br>
> + .is_enabled = ast2700_clk_is_enabled,<br>
> +};<br>
> +<br>
> +static struct clk_hw *ast2700_clk_hw_register_gate(struct device *dev, const<br>
> char *name,<br>
> + const struct clk_parent_data *parent,<br>
> + void __iomem *reg, u8 clock_idx,<br>
> + unsigned long clk_gate_flags, spinlock_t<br>
> *lock) {<br>
> + struct clk_gate *gate;<br>
> + struct clk_hw *hw;<br>
> + struct clk_init_data init;<br>
> + int ret = -EINVAL;<br>
> +<br>
> + gate = kzalloc(sizeof(*gate), GFP_KERNEL);<br>
> + if (!gate)<br>
> + return ERR_PTR(-ENOMEM);<br>
> +<br>
> + <a href="http://init.name" rel="noreferrer" target="_blank">init.name</a> = name;<br>
> + init.ops = &ast2700_clk_gate_ops;<br>
> + init.flags = clk_gate_flags;<br>
> + init.parent_names = parent ? &parent->name : NULL;<br>
> + init.num_parents = parent ? 1 : 0;<br>
> +<br>
> + gate->reg = reg;<br>
> + gate->bit_idx = clock_idx;<br>
> + gate->flags = 0;<br>
> + gate->lock = lock;<br>
> + gate->hw.init = &init;<br>
> +<br>
> + hw = &gate->hw;<br>
> + ret = clk_hw_register(dev, hw);<br>
> + if (ret) {<br>
> + kfree(gate);<br>
> + hw = ERR_PTR(ret);<br>
> + }<br>
> +<br>
> + return hw;<br>
> +}<br>
> +<br>
> +static void ast2700_soc1_configure_i3c_clk(struct ast2700_clk_ctrl<br>
> +*clk_ctrl) {<br>
> + if (readl(clk_ctrl->base + SCU1_REVISION_ID) & REVISION_ID)<br>
> + /* I3C 250MHz = HPLL/4 */<br>
> + writel((readl(clk_ctrl->base + SCU1_CLK_SEL2) &<br>
> + ~SCU1_CLK_I3C_DIV_MASK) |<br>
> + FIELD_PREP(SCU1_CLK_I3C_DIV_MASK,<br>
> + SCU1_CLK_I3C_DIV(4)),<br>
> + clk_ctrl->base + SCU1_CLK_SEL2); }<br>
> +<br>
> +static int ast2700_soc_clk_probe(struct platform_device *pdev) {<br>
> + const struct ast2700_clk_data *clk_data;<br>
> + struct clk_hw_onecell_data *clk_hw_data;<br>
> + struct ast2700_clk_ctrl *clk_ctrl;<br>
> + struct device *dev = &pdev->dev;<br>
> + struct auxiliary_device *adev;<br>
> + void __iomem *clk_base;<br>
> + struct clk_hw **hws;<br>
> + char *reset_name;<br>
> + int ret;<br>
> + int i;<br>
> +<br>
> + clk_ctrl = devm_kzalloc(dev, sizeof(*clk_ctrl), GFP_KERNEL);<br>
> + if (!clk_ctrl)<br>
> + return -ENOMEM;<br>
> + clk_ctrl->dev = dev;<br>
> + dev_set_drvdata(&pdev->dev, clk_ctrl);<br>
> +<br>
> + spin_lock_init(&clk_ctrl->lock);<br>
> +<br>
> + clk_base = devm_platform_ioremap_resource(pdev, 0);<br>
> + if (IS_ERR(clk_base))<br>
> + return PTR_ERR(clk_base);<br>
> +<br>
> + clk_ctrl->base = clk_base;<br>
> +<br>
> + clk_data = device_get_match_data(dev);<br>
> + if (!clk_data)<br>
> + return -ENODEV;<br>
> +<br>
> + clk_ctrl->clk_data = clk_data;<br>
> + reset_name = devm_kasprintf(dev, GFP_KERNEL, "reset%d",<br>
> +clk_data->scu);<br>
> +<br>
> + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,<br>
> clk_data->nr_clks),<br>
> + GFP_KERNEL);<br>
> + if (!clk_hw_data)<br>
> + return -ENOMEM;<br>
> +<br>
> + clk_hw_data->num = clk_data->nr_clks;<br>
> + hws = clk_hw_data->hws;<br>
> +<br>
> + if (clk_data->scu)<br>
> + ast2700_soc1_configure_i3c_clk(clk_ctrl);<br>
> +<br>
> + for (i = 0; i < clk_data->nr_clks; i++) {<br>
> + const struct ast2700_clk_info *clk = &clk_data->clk_info[i];<br>
> + void __iomem *reg;<br>
> +<br>
> + if (clk->type == CLK_FIXED) {<br>
> + const struct ast2700_clk_fixed_rate_data *fixed_rate =<br>
> +&clk->data.rate;<br>
> +<br>
> + hws[i] = devm_clk_hw_register_fixed_rate(dev, clk->name,<br>
> NULL, 0,<br>
> + fixed_rate->fixed_rate);<br>
> + } else if (clk->type == CLK_FIXED_FACTOR) {<br>
> + const struct ast2700_clk_fixed_factor_data *factor =<br>
> +&clk->data.factor;<br>
> +<br>
> + hws[i] = devm_clk_hw_register_fixed_factor(dev, clk->name,<br>
> + factor->parent->name,<br>
> + 0, factor->mult, factor->div);<br>
> + } else if (clk->type == DCLK_FIXED) {<br>
> + const struct ast2700_clk_pll_data *pll = &clk->data.pll;<br>
> +<br>
> + reg = clk_ctrl->base + pll->reg;<br>
> + hws[i] = ast2700_clk_hw_register_dclk(reg, clk->name,<br>
> clk_ctrl);<br>
> + } else if (clk->type == CLK_HPLL) {<br>
> + const struct ast2700_clk_pll_data *pll = &clk->data.pll;<br>
> +<br>
> + reg = clk_ctrl->base + pll->reg;<br>
> + hws[i] = ast2700_clk_hw_register_hpll(reg, clk->name,<br>
> + pll->parent->name, clk_ctrl);<br>
> + } else if (clk->type == CLK_PLL) {<br>
> + const struct ast2700_clk_pll_data *pll = &clk->data.pll;<br>
> +<br>
> + reg = clk_ctrl->base + pll->reg;<br>
> + hws[i] = ast2700_clk_hw_register_pll(i, reg, clk->name,<br>
> + pll->parent->name, clk_ctrl);<br>
> + } else if (clk->type == CLK_UART_PLL) {<br>
> + const struct ast2700_clk_pll_data *pll = &clk->data.pll;<br>
> +<br>
> + reg = clk_ctrl->base + pll->reg;<br>
> + hws[i] = ast2700_clk_hw_register_uartpll(reg, clk->name,<br>
> + pll->parent->name, clk_ctrl);<br>
> + } else if (clk->type == CLK_MUX) {<br>
> + const struct ast2700_clk_mux_data *mux = &clk->data.mux;<br>
> +<br>
> + reg = clk_ctrl->base + mux->reg;<br>
> + hws[i] = devm_clk_hw_register_mux_parent_data_table(dev,<br>
> clk->name,<br>
> + mux->parents,<br>
> + mux->num_parents, 0,<br>
> + reg, mux->bit_shift,<br>
> + mux->bit_width, 0,<br>
> + NULL, &clk_ctrl->lock);<br>
> + } else if (clk->type == CLK_MISC) {<br>
> + const struct ast2700_clk_pll_data *misc = &clk->data.pll;<br>
> +<br>
> + reg = clk_ctrl->base + misc->reg;<br>
> + hws[i] = ast2700_clk_hw_register_misc(i, reg, clk->name,<br>
> + misc->parent->name, clk_ctrl);<br>
> + } else if (clk->type == CLK_DIVIDER) {<br>
> + const struct ast2700_clk_div_data *div = &clk->data.div;<br>
> +<br>
> + reg = clk_ctrl->base + div->reg;<br>
> + hws[i] = devm_clk_hw_register_divider_table(dev, clk->name,<br>
> + div->parent->name, 0,<br>
> + reg, div->bit_shift,<br>
> + div->bit_width, 0,<br>
> + div->div_table,<br>
> + &clk_ctrl->lock);<br>
> + } else if (clk->type == CLK_GATE_ASPEED) {<br>
> + const struct ast2700_clk_gate_data *gate = &clk->data.gate;<br>
> +<br>
> + reg = clk_ctrl->base + gate->reg;<br>
> + hws[i] = ast2700_clk_hw_register_gate(dev, clk->name,<br>
> gate->parent,<br>
> + reg, gate->bit, gate->flags,<br>
> + &clk_ctrl->lock);<br>
> +<br>
> + } else {<br>
> + const struct ast2700_clk_gate_data *gate = &clk->data.gate;<br>
> +<br>
> + reg = clk_ctrl->base + gate->reg;<br>
> + hws[i] = devm_clk_hw_register_gate_parent_data(dev,<br>
> clk->name, gate->parent,<br>
> + 0, reg, clk->clk_idx, 0,<br>
> + &clk_ctrl->lock);<br>
> + }<br>
> +<br>
> + if (IS_ERR(hws[i]))<br>
> + return PTR_ERR(hws[i]);<br>
> + }<br>
> +<br>
> + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,<br>
> clk_hw_data);<br>
> + if (ret)<br>
> + return ret;<br>
> +<br>
> + adev = devm_auxiliary_device_create(dev, reset_name, (__force void<br>
> *)clk_base);<br>
> + if (!adev)<br>
> + return -ENODEV;<br>
> +<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static const struct ast2700_clk_data ast2700_clk0_data = {<br>
> + .scu = 0,<br>
> + .nr_clks = ARRAY_SIZE(ast2700_scu0_clk_info),<br>
> + .clk_info = ast2700_scu0_clk_info,<br>
> +};<br>
> +<br>
> +static const struct ast2700_clk_data ast2700_clk1_data = {<br>
> + .scu = 1,<br>
> + .nr_clks = ARRAY_SIZE(ast2700_scu1_clk_info),<br>
> + .clk_info = ast2700_scu1_clk_info,<br>
> +};<br>
> +<br>
> +static const struct of_device_id ast2700_scu_match[] = {<br>
> + { .compatible = "aspeed,ast2700-scu0", .data = &ast2700_clk0_data },<br>
> + { .compatible = "aspeed,ast2700-scu1", .data = &ast2700_clk1_data },<br>
> + { /* sentinel */ }<br>
> +};<br>
> +<br>
> +MODULE_DEVICE_TABLE(of, ast2700_scu_match);<br>
> +<br>
> +static struct platform_driver ast2700_scu_driver = {<br>
> + .probe = ast2700_soc_clk_probe,<br>
> + .driver = {<br>
> + .name = "clk-ast2700",<br>
> + .of_match_table = ast2700_scu_match,<br>
> + },<br>
> +};<br>
> +<br>
> +static int __init clk_ast2700_init(void) {<br>
> + return platform_driver_register(&ast2700_scu_driver);<br>
> +}<br>
> +arch_initcall(clk_ast2700_init);<br>
> --<br>
> 2.34.1<br>
<br>
</blockquote></div>