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Hi Krzk,</div>
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I will speperate clock part in the v3 patch into Ryan's clock series.</div>
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>So you did not write commit msgs to none of the commits?</div>
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>> ---</div>
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>> drivers/clk/Makefile | 1 +</div>
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>> drivers/clk/clk-ast2700.c | 1166 +++++++++++++++++++++++++++++++++++++</div>
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>> 2 files changed, 1167 insertions(+)</div>
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>> create mode 100644 drivers/clk/clk-ast2700.c</div>
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>></div>
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>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile</div>
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>> index f793a16cad40..0d5992ea0fa4 100644</div>
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>> --- a/drivers/clk/Makefile</div>
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>> +++ b/drivers/clk/Makefile</div>
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>> @@ -38,6 +38,7 @@ obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o</div>
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>> obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o</div>
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>> obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o</div>
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>> obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o</div>
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>> +obj-$(CONFIG_MACH_ASPEED_G7) += clk-ast2700.o</div>
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>...</div>
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>> +</div>
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>> +static const char *const pspclk_sel[] = {</div>
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>> + "soc0-mpll",</div>
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>> + "soc0-hpll",</div>
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>> +};</div>
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>> +</div>
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>> +static const char *const soc0_uartclk_sel[] = {</div>
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>> + "soc0-clk24Mhz",</div>
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>> + "soc0-clk192Mhz",</div>
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>> +};</div>
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>> +</div>
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>> +static const char *const emmcclk_sel[] = {</div>
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>> + "soc0-mpll_div4",</div>
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>> + "soc0-hpll_div4",</div>
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>> +};</div>
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>> +</div>
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>> +static int ast2700_soc0_clk_init(struct device_node *soc0_node)</div>
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>> +{</div>
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>> + struct clk_hw_onecell_data *clk_data;</div>
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>> + void __iomem *clk_base;</div>
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>> + struct ast2700_reset *reset;</div>
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>> + struct clk_hw **clks;</div>
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>> + int div;</div>
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>> + u32 val;</div>
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>> + int ret;</div>
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>> +</div>
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>> + clk_data = kzalloc(struct_size(clk_data, hws, SOC0_NUM_CLKS), GFP_KERNEL);</div>
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>> + if (!clk_data)</div>
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>> + return -ENOMEM;</div>
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>> +</div>
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>> + clk_data->num = SOC0_NUM_CLKS;</div>
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>> + clks = clk_data->hws;</div>
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>> +</div>
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>> + clk_base = of_iomap(soc0_node, 0);</div>
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>> + if (WARN_ON(IS_ERR(clk_base)))</div>
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>Drop WARN_ON</div>
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I remind Ryan for this fix. He will reply in these series.</div>
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<a href="https://patchwork.kernel.org/project/linux-clk/patch/20240808075937.2756733-5-ryan_chen@aspeedtech.com/" id="OWAb71c9975-6163-984c-09f3-6224bf53cede" class="OWAAutoLink">[4/4] dt-bindings: clock: Add AST2700 clock bindings - Patchwork (kernel.org)</a></div>
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<br>
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>> + return PTR_ERR(clk_base);</div>
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>> +</div>
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>> + reset = kzalloc(sizeof(*reset), GFP_KERNEL);</div>
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>> + if (!reset)</div>
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>> + return -ENOMEM;</div>
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>> +</div>
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>> + reset->base = clk_base;</div>
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>> +</div>
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>> + reset->rcdev.owner = THIS_MODULE;</div>
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>> + reset->rcdev.nr_resets = SOC0_RESET_NUMS;</div>
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>> + reset->rcdev.ops = &ast2700_reset_ops;</div>
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>> + reset->rcdev.of_node = soc0_node;</div>
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>> +</div>
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>> + ret = reset_controller_register(&reset->rcdev);</div>
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>> + if (ret) {</div>
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>> + pr_err("soc0 failed to register reset controller\n");</div>
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>> + return ret;</div>
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>> + }</div>
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>> +</div>
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>> + //refclk</div>
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></div>
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>Weird comment. Please read Coding Style.</div>
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I remind Ryan for this fix. He will reply in these series.</div>
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<a href="https://patchwork.kernel.org/project/linux-clk/patch/20240808075937.2756733-5-ryan_chen@aspeedtech.com/" id="OWA704b0821-8f44-4ea3-d387-0cf0ee8d11df" class="OWAAutoLink" style="margin: 0px;">[4/4] dt-bindings: clock: Add AST2700 clock bindings - Patchwork
(kernel.org)</a></div>
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<br>
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>> + clks[SCU0_CLKIN] =</div>
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>> + clk_hw_register_fixed_rate(NULL, "soc0-clkin", NULL, 0, SCU_CLK_25MHZ);</div>
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>> +</div>
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>> + clks[SCU0_CLK_24M] =</div>
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>> + clk_hw_register_fixed_rate(NULL, "soc0-clk24Mhz", NULL, 0, SCU_CLK_24MHZ);</div>
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>> +</div>
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>> + clks[SCU0_CLK_192M] =</div>
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>> + clk_hw_register_fixed_rate(NULL, "soc0-clk192Mhz", NULL, 0, SCU_CLK_192MHZ);</div>
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>> +</div>
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>> + //hpll</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + val = readl(clk_base + SCU0_HWSTRAP1);</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + if ((val & GENMASK(3, 2)) != 0) {</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + switch ((val & GENMASK(3, 2)) >> 2) {</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + case 1:</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + clks[SCU0_CLK_HPLL] =</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + clk_hw_register_fixed_rate(NULL, "soc0-hpll", NULL, 0, 1900000000);</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + break;</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + case 2:</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + clks[SCU0_CLK_HPLL] =</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + clk_hw_register_fixed_rate(NULL, "soc0-hpll", NULL, 0, 1800000000);</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + break;</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + case 3:</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + clks[SCU0_CLK_HPLL] =</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + clk_hw_register_fixed_rate(NULL, "soc0-hpll", NULL, 0, 1700000000);</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + break;</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + }</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + } else {</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + val = readl(clk_base + SCU0_HPLL_PARAM);</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + clks[SCU0_CLK_HPLL] = ast2700_soc0_hw_pll("soc0-hpll", "soc0-clkin", val);</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + }</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + clks[SCU0_CLK_HPLL_DIV2] = clk_hw_register_fixed_factor(NULL, "soc0-hpll_div2", "soc0-hpll", 0, 1, 2);</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + clks[SCU0_CLK_HPLL_DIV4] = clk_hw_register_fixed_factor(NULL, "soc0-hpll_div4", "soc0-hpll", 0, 1, 4);</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> +</div>
<div style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
>> + //dpll</div>
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></div>
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<br>
</div>
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--</div>
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Best Regards,</div>
<div class="elementToProof" style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">
Kevin. Chen</div>
<div id="appendonsend"></div>
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<br>
</div>
<hr style="display: inline-block; width: 98%;">
<div id="divRplyFwdMsg" dir="ltr"><span style="font-family: Calibri, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);"><b>寄件者:</b> Krzysztof Kozlowski <krzk@kernel.org><br>
<b>寄件日期:</b> 2024年7月26日 下午 07:13<br>
<b>收件者:</b> Kevin Chen <kevin_chen@aspeedtech.com>; robh@kernel.org <robh@kernel.org>; krzk+dt@kernel.org <krzk+dt@kernel.org>; conor+dt@kernel.org <conor+dt@kernel.org>; joel@jms.id.au <joel@jms.id.au>; andrew@codeconstruct.com.au <andrew@codeconstruct.com.au>;
lee@kernel.org <lee@kernel.org>; catalin.marinas@arm.com <catalin.marinas@arm.com>; will@kernel.org <will@kernel.org>; arnd@arndb.de <arnd@arndb.de>; olof@lixom.net <olof@lixom.net>; soc@kernel.org <soc@kernel.org>; mturquette@baylibre.com <mturquette@baylibre.com>;
sboyd@kernel.org <sboyd@kernel.org>; p.zabel@pengutronix.de <p.zabel@pengutronix.de>; quic_bjorande@quicinc.com <quic_bjorande@quicinc.com>; geert+renesas@glider.be <geert+renesas@glider.be>; dmitry.baryshkov@linaro.org <dmitry.baryshkov@linaro.org>; shawnguo@kernel.org
<shawnguo@kernel.org>; neil.armstrong@linaro.org <neil.armstrong@linaro.org>; m.szyprowski@samsung.com <m.szyprowski@samsung.com>; nfraprado@collabora.com <nfraprado@collabora.com>; u-kumar1@ti.com <u-kumar1@ti.com>; devicetree@vger.kernel.org <devicetree@vger.kernel.org>;
linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>; linux-aspeed@lists.ozlabs.org <linux-aspeed@lists.ozlabs.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; linux-clk@vger.kernel.org <linux-clk@vger.kernel.org><br>
<b>主旨:</b> Re: [PATCH v1 03/10] clk: ast2700: add clock controller</span>
<div> </div>
</div>
<div style="font-size: 11pt;">On 26/07/2024 13:03, Kevin Chen wrote:<br>
> Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com><br>
<br>
So you did not write commit msgs to none of the commits?<br>
<br>
> ---<br>
> drivers/clk/Makefile | 1 +<br>
> drivers/clk/clk-ast2700.c | 1166 +++++++++++++++++++++++++++++++++++++<br>
> 2 files changed, 1167 insertions(+)<br>
> create mode 100644 drivers/clk/clk-ast2700.c<br>
><br>
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile<br>
> index f793a16cad40..0d5992ea0fa4 100644<br>
> --- a/drivers/clk/Makefile<br>
> +++ b/drivers/clk/Makefile<br>
> @@ -38,6 +38,7 @@ obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o<br>
> obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o<br>
> obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o<br>
> obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o<br>
> +obj-$(CONFIG_MACH_ASPEED_G7) += clk-ast2700.o<br>
<br>
...<br>
<br>
> +<br>
> +static const char *const pspclk_sel[] = {<br>
> + "soc0-mpll",<br>
> + "soc0-hpll",<br>
> +};<br>
> +<br>
> +static const char *const soc0_uartclk_sel[] = {<br>
> + "soc0-clk24Mhz",<br>
> + "soc0-clk192Mhz",<br>
> +};<br>
> +<br>
> +static const char *const emmcclk_sel[] = {<br>
> + "soc0-mpll_div4",<br>
> + "soc0-hpll_div4",<br>
> +};<br>
> +<br>
> +static int ast2700_soc0_clk_init(struct device_node *soc0_node)<br>
> +{<br>
> + struct clk_hw_onecell_data *clk_data;<br>
> + void __iomem *clk_base;<br>
> + struct ast2700_reset *reset;<br>
> + struct clk_hw **clks;<br>
> + int div;<br>
> + u32 val;<br>
> + int ret;<br>
> +<br>
> + clk_data = kzalloc(struct_size(clk_data, hws, SOC0_NUM_CLKS), GFP_KERNEL);<br>
> + if (!clk_data)<br>
> + return -ENOMEM;<br>
> +<br>
> + clk_data->num = SOC0_NUM_CLKS;<br>
> + clks = clk_data->hws;<br>
> +<br>
> + clk_base = of_iomap(soc0_node, 0);<br>
> + if (WARN_ON(IS_ERR(clk_base)))<br>
<br>
Drop WARN_ON<br>
<br>
> + return PTR_ERR(clk_base);<br>
> +<br>
> + reset = kzalloc(sizeof(*reset), GFP_KERNEL);<br>
> + if (!reset)<br>
> + return -ENOMEM;<br>
> +<br>
> + reset->base = clk_base;<br>
> +<br>
> + reset->rcdev.owner = THIS_MODULE;<br>
> + reset->rcdev.nr_resets = SOC0_RESET_NUMS;<br>
> + reset->rcdev.ops = &ast2700_reset_ops;<br>
> + reset->rcdev.of_node = soc0_node;<br>
> +<br>
> + ret = reset_controller_register(&reset->rcdev);<br>
> + if (ret) {<br>
> + pr_err("soc0 failed to register reset controller\n");<br>
> + return ret;<br>
> + }<br>
> +<br>
> + //refclk<br>
<br>
Weird comment. Please read Coding Style.<br>
<br>
<br>
> + clks[SCU0_CLKIN] =<br>
> + clk_hw_register_fixed_rate(NULL, "soc0-clkin", NULL, 0, SCU_CLK_25MHZ);<br>
> +<br>
> + clks[SCU0_CLK_24M] =<br>
> + clk_hw_register_fixed_rate(NULL, "soc0-clk24Mhz", NULL, 0, SCU_CLK_24MHZ);<br>
> +<br>
> + clks[SCU0_CLK_192M] =<br>
> + clk_hw_register_fixed_rate(NULL, "soc0-clk192Mhz", NULL, 0, SCU_CLK_192MHZ);<br>
> +<br>
> + //hpll<br>
> + val = readl(clk_base + SCU0_HWSTRAP1);<br>
> + if ((val & GENMASK(3, 2)) != 0) {<br>
> + switch ((val & GENMASK(3, 2)) >> 2) {<br>
> + case 1:<br>
> + clks[SCU0_CLK_HPLL] =<br>
> + clk_hw_register_fixed_rate(NULL, "soc0-hpll", NULL, 0, 1900000000);<br>
> + break;<br>
> + case 2:<br>
> + clks[SCU0_CLK_HPLL] =<br>
> + clk_hw_register_fixed_rate(NULL, "soc0-hpll", NULL, 0, 1800000000);<br>
> + break;<br>
> + case 3:<br>
> + clks[SCU0_CLK_HPLL] =<br>
> + clk_hw_register_fixed_rate(NULL, "soc0-hpll", NULL, 0, 1700000000);<br>
> + break;<br>
> + }<br>
> + } else {<br>
> + val = readl(clk_base + SCU0_HPLL_PARAM);<br>
> + clks[SCU0_CLK_HPLL] = ast2700_soc0_hw_pll("soc0-hpll", "soc0-clkin", val);<br>
> + }<br>
> + clks[SCU0_CLK_HPLL_DIV2] = clk_hw_register_fixed_factor(NULL, "soc0-hpll_div2", "soc0-hpll", 0, 1, 2);<br>
> + clks[SCU0_CLK_HPLL_DIV4] = clk_hw_register_fixed_factor(NULL, "soc0-hpll_div4", "soc0-hpll", 0, 1, 4);<br>
> +<br>
> + //dpll<br>
<br>
<br>
<br>
Best regards,<br>
Krzysztof<br>
<br>
</div>
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