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Hi Krzk,</div>
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In ASPEED, ast2400/2500/2600 use arm architecture with KCONFIG_ARCH_ASPEED which slect MACH_ASPEED_G4/G5/G6 in arch/arm/mach-aspeed/Kconfig.</div>
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In the fureture, there would be ast2800/2900/... using arm64. We need to clarify the IC generation between 7th/8th/9th/....</div>
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Maybe change ARCH_ASPEED/MACH_ASPEEDG<i>7 to </i>ARCH_ASPEED first.</div>
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Or, do you have better Kconfig usage?</div>
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<pre style="margin: 0px 0px 10px; padding: 9.5px; border-radius: 0px; display: block;"><div class="elementToProof" style="text-align: left; text-indent: 0px; line-height: 14.3px; font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);">> +config ARCH_ASPEED
> + bool "Aspeed SoC family"
> + select MACH_ASPEED_G7
> + help
> + Say yes if you intend to run on an Aspeed ast2700 or similar
> + seventh generation Aspeed BMCs.
> +
> +config MACH_ASPEED_G7
> + bool "Aspeed SoC AST2700"
There are no MACHines for arm64. Look at this code. Do you see MACH
anywhere else? No. Then why Aspeed must be different?</div></pre>
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--</div>
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Best Regards,</div>
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Kevin. Chen</div>
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<div id="divRplyFwdMsg" dir="ltr"><span style="font-family: Calibri, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);"><b>寄件者:</b> Krzysztof Kozlowski <krzk@kernel.org><br>
<b>寄件日期:</b> 2024年8月13日 下午 04:50<br>
<b>收件者:</b> Kevin Chen <kevin_chen@aspeedtech.com>; tglx@linutronix.de <tglx@linutronix.de>; robh@kernel.org <robh@kernel.org>; krzk+dt@kernel.org <krzk+dt@kernel.org>; conor+dt@kernel.org <conor+dt@kernel.org>; joel@jms.id.au <joel@jms.id.au>; andrew@codeconstruct.com.au
<andrew@codeconstruct.com.au>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; devicetree@vger.kernel.org <devicetree@vger.kernel.org>; linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>; linux-aspeed@lists.ozlabs.org
<linux-aspeed@lists.ozlabs.org><br>
<b>主旨:</b> Re: [PATCH v1 2/2] irqchip/aspeed-intc: Add support for 10 INTC interrupts on AST27XX platforms</span>
<div> </div>
</div>
<div style="font-size: 11pt;">On 13/08/2024 09:43, Kevin Chen wrote:<br>
> There are 10 interrupt source of soc0_intc in CPU die INTC.<br>
> 1. 6 interrupt sources in IO die of soc1_intc0~soc1_intc5.<br>
> 2. 2 interrupt sources in LTPI of ltpi0_intc0 and ltpi0_intc1.<br>
> 3. 2 interrupt sources in LTPI of ltpi1_intc0 and ltpi1_intc1.<br>
> Request GIC interrupt to check each bit in status register to do next<br>
> level INTC handler.<br>
><br>
> In next level INTC handler of IO die or LTPI INTC using soc1_intcX combining<br>
> 32 interrupt sources into soc0_intc11 in CPU die. In soc1_intcX, handler<br>
> would check 32 bit of status register to do the requested device<br>
> handler.<br>
> ---<br>
> drivers/irqchip/Makefile | 1 +<br>
> drivers/irqchip/irq-aspeed-intc.c | 198 ++++++++++++++++++++++++++++++<br>
> 2 files changed, 199 insertions(+)<br>
> create mode 100644 drivers/irqchip/irq-aspeed-intc.c<br>
><br>
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile<br>
> index 15635812b2d6..d2fe686ae018 100644<br>
> --- a/drivers/irqchip/Makefile<br>
> +++ b/drivers/irqchip/Makefile<br>
> @@ -84,6 +84,7 @@ obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o<br>
> obj-$(CONFIG_LS_EXTIRQ) += irq-ls-extirq.o<br>
> obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o<br>
> obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o<br>
> +obj-$(CONFIG_MACH_ASPEED_G7) += irq-aspeed-intc.o<br>
<br>
There is no such thing as CONFIG_MACH_ASPEED_G7. And there will never be.<br>
<br>
You already received feedback on this, so why do you keep pushing your<br>
solution? You did not respond to any feedback given, just send the same<br>
and the same till we agree?<br>
<br>
NAK.<br>
<br>
> obj-$(CONFIG_STM32MP_EXTI) += irq-stm32mp-exti.o<br>
> obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o<br>
> obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o<br>
> diff --git a/drivers/irqchip/irq-aspeed-intc.c b/drivers/irqchip/irq-aspeed-intc.c<br>
> new file mode 100644<br>
> index 000000000000..71407475fb27<br>
<br>
...<br>
<br>
> +static int __init aspeed_intc_ic_of_init_v2(struct device_node *node,<br>
> + struct device_node *parent)<br>
> +{<br>
> + struct aspeed_intc_ic *intc_ic;<br>
> + int ret = 0;<br>
> + int irq, i;<br>
> +<br>
> + intc_ic = kzalloc(sizeof(*intc_ic), GFP_KERNEL);<br>
> + if (!intc_ic)<br>
> + return -ENOMEM;<br>
> +<br>
> + intc_ic->base = of_iomap(node, 0);<br>
> + if (!intc_ic->base) {<br>
> + pr_err("Failed to iomap intc_ic base\n");<br>
> + ret = -ENOMEM;<br>
> + goto err_free_ic;<br>
> + }<br>
> + writel(0xffffffff, intc_ic->base + INTC_INT_STATUS_REG);<br>
> + writel(0x0, intc_ic->base + INTC_INT_ENABLE_REG);<br>
> +<br>
> + intc_ic->irq_domain = irq_domain_add_linear(node, 32,<br>
> + &aspeed_intc_ic_irq_domain_ops, intc_ic);<br>
> + if (!intc_ic->irq_domain) {<br>
> + ret = -ENOMEM;<br>
> + goto err_iounmap;<br>
> + }<br>
> +<br>
> + raw_spin_lock_init(&intc_ic->gic_lock);<br>
> + raw_spin_lock_init(&intc_ic->intc_lock);<br>
> +<br>
> + intc_ic->irq_domain->name = "aspeed-intc-domain";<br>
> +<br>
> + for (i = 0; i < of_irq_count(node); i++) {<br>
> + irq = irq_of_parse_and_map(node, i);<br>
> + if (!irq) {<br>
> + pr_err("Failed to get irq number\n");<br>
> + ret = -EINVAL;<br>
> + goto err_iounmap;<br>
> + } else {<br>
> + irq_set_chained_handler_and_data(irq, aspeed_intc_ic_irq_handler, intc_ic);<br>
> + }<br>
> + }<br>
> +<br>
> + return 0;<br>
> +<br>
> +err_iounmap:<br>
> + iounmap(intc_ic->base);<br>
> +err_free_ic:<br>
> + kfree(intc_ic);<br>
> + return ret;<br>
> +}<br>
<br>
Don't duplicate code. These are almost the same, so define one function<br>
which is then called by aspeed_intc_ic_of_init and<br>
aspeed_intc_ic_of_init_v2.<br>
<br>
> +<br>
> +IRQCHIP_DECLARE(ast2700_intc_ic, "aspeed,ast2700-intc-1.0", aspeed_intc_ic_of_init);<br>
> +IRQCHIP_DECLARE(ast2700_intc_icv2, "aspeed,ast2700-intc-2.0", aspeed_intc_ic_of_init_v2);<br>
<br>
Best regards,<br>
Krzysztof<br>
<br>
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