<font color="#663366"><font><font face="verdana,sans-serif"><br></font></font></font><div class="gmail_quote">On 17 May 2013 15:40, Naveen Krishna Chatradhi <span dir="ltr"><<a href="mailto:ch.naveen@samsung.com" target="_blank">ch.naveen@samsung.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div>Adds support for High Speed I2C driver found in Exynos5 and<br>
later SoCs from Samsung.<br>
<br>
</div><div>Driver only supports Device Tree method.<br>
<br>
</div><div>Changes since v1:<br>
1. Added FIFO functionality<br>
2. Added High speed mode functionality<br>
3. Remove SMBUS_QUICK<br>
4. Remove the debugfs functionality<br>
5. Use devm_* functions where ever possible<br>
</div>6. Driver is free from GPIO configs (only supports pinctrl method)<br>
<div>7. Use OF data string "clock-frequency" to get the bus operating frequencies<br>
8. Split the clock divisor calculation function<br>
9. Add resets for the failed transacton cases<br>
10. few other bug fixes and cosmetic changes<br>
<br>
</div><div>Signed-off-by: Taekgyun Ko <<a href="mailto:taeggyun.ko@samsung.com" target="_blank">taeggyun.ko@samsung.com</a>><br>
Signed-off-by: Naveen Krishna Chatradhi <<a href="mailto:ch.naveen@samsung.com" target="_blank">ch.naveen@samsung.com</a>><br>
</div><div>Reviewed-by: Simon Glass <<a href="mailto:sjg@google.com" target="_blank">sjg@google.com</a>><br>
Tested-by: Andrew Bresticker <<a href="mailto:abrestic@google.com" target="_blank">abrestic@google.com</a>><br>
Signed-off-by: Yuvaraj Kumar C D <<a href="mailto:yuvaraj.cd@samsung.com" target="_blank">yuvaraj.cd@samsung.com</a>><br>
Signed-off-by: Andrew Bresticker <<a href="mailto:abrestic@google.com" target="_blank">abrestic@google.com</a>><br></div></blockquote><div><br></div><div>Hello Wolfram,</div><div><br></div><div>This driver was submitted, reviewed several times.</div>
<div>and been improved as we were using it.</div><div><br></div><div>I did not see any review comments on this driver.</div><div>Can we get this merged or Should we wait for few more reviews ?</div><div><br></div><div>Thanks & Regards,</div>
<div>Naveen Krishna</div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div>
---<br>
<br>
</div>Changes since v8<br>
1. improved the device tree bindings description page for i2c-exynos5<br>
2. fixed the return value check for devm_ioremap_resource<br>
<br>
.../devicetree/bindings/i2c/i2c-exynos5.txt | 45 +<br>
<div> drivers/i2c/busses/Kconfig | 7 +<br>
drivers/i2c/busses/Makefile | 1 +<br>
</div> drivers/i2c/busses/i2c-exynos5.c | 888 ++++++++++++++++++++<br>
4 files changed, 941 insertions(+)<br>
<div> create mode 100644 Documentation/devicetree/bindings/i2c/i2c-exynos5.txt<br>
create mode 100644 drivers/i2c/busses/i2c-exynos5.c<br>
<br>
diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt<br>
</div>new file mode 100644<br>
index 0000000..29c01c0<br>
--- /dev/null<br>
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt<br>
@@ -0,0 +1,45 @@<br>
<div>+* Samsung's High Speed I2C controller<br>
+<br>
+The Samsung's High Speed I2C controller is used to interface with I2C devices<br>
+at various speeds ranging from 100khz to 3.4Mhz.<br>
+<br>
+Required properties:<br>
+ - compatible: value should be.<br>
</div>+ -> "samsung,exynos5-hsi2c", for i2c compatible with exynos5 hsi2c.<br>
<div>+ - reg: physical base address of the controller and length of memory mapped<br>
+ region.<br>
+ - interrupts: interrupt number to the cpu.<br>
</div>+ - #address-cells: always 1 (for i2c addresses)<br>
+ - #size-cells: always 0<br>
+<br>
+ - Pinctrl:<br>
<div>+ - pinctrl-0: Pin control group to be used for this controller.<br>
+ - pinctrl-names: Should contain only one value - "default".<br>
</div><div><div>+<br>
+Optional properties:<br>
+ - samsung,hs-mode: Mode of operation, High speed or Fast speed mode. If not<br>
+ specified, default value is 0.<br>
+ - clock-frequency: Desired operating frequency in Hz of the bus.<br>
+ If not specified, the default value in Hz is 100000.<br>
+<br>
+Example:<br>
+<br>
+hsi2c@12ca0000 {<br>
+ compatible = "samsung,exynos5-hsi2c";<br>
+ reg = <0x12ca0000 0x100>;<br>
+ interrupts = <56>;<br>
+ clock-frequency = <100000>;<br>
+<br>
+ /* Pinctrl variant begins here */<br>
+ pinctrl-0 = <&i2c4_bus>;<br>
+ pinctrl-names = "default";<br>
+ /* Pinctrl variant ends here */<br>
+<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+<br>
+ s2mps11_pmic@66 {<br>
+ compatible = "samsung,s2mps11-pmic";<br>
+ reg = <0x66>;<br>
+ };<br>
+};<br>
</div></div>diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig<br>
index adfee98..49a665f 100644<br>
--- a/drivers/i2c/busses/Kconfig<br>
+++ b/drivers/i2c/busses/Kconfig<br>
<div>@@ -434,6 +434,13 @@ config I2C_EG20T<br>
ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.<br>
ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.<br>
<br>
</div>+config I2C_EXYNOS5<br>
<div>+ tristate "Exynos5 high-speed I2C driver"<br>
+ depends on ARCH_EXYNOS5 && OF<br>
</div>+ help<br>
<div>+ Say Y here to include support for high-speed I2C controller in the<br>
+ Exynos5 based Samsung SoCs.<br>
+<br>
config I2C_GPIO<br>
tristate "GPIO-based bitbanging I2C"<br>
depends on GENERIC_GPIO<br>
</div>diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile<br>
index 8f4fc23..b19366c 100644<br>
--- a/drivers/i2c/busses/Makefile<br>
+++ b/drivers/i2c/busses/Makefile<br>
<div>@@ -42,6 +42,7 @@ i2c-designware-platform-objs := i2c-designware-platdrv.o<br>
obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o<br>
i2c-designware-pci-objs := i2c-designware-pcidrv.o<br>
obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o<br>
+obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o<br>
obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o<br>
obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o<br>
obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o<br>
</div><div>diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c<br>
new file mode 100644<br>
</div>index 0000000..33c481d<br>
--- /dev/null<br>
+++ b/drivers/i2c/busses/i2c-exynos5.c<br>
<div>@@ -0,0 +1,888 @@<br>
+/**<br>
+ * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver<br>
</div>+ *<br>
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.<br>
+ *<br>
<div>+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License version 2 as<br>
+ * published by the Free Software Foundation.<br>
+*/<br>
+<br>
+#include <linux/kernel.h><br>
+#include <linux/module.h><br>
+<br>
+#include <linux/i2c.h><br>
+#include <linux/init.h><br>
+#include <linux/time.h><br>
+#include <linux/interrupt.h><br>
+#include <linux/delay.h><br>
+#include <linux/errno.h><br>
+#include <linux/err.h><br>
+#include <linux/platform_device.h><br>
</div>+#include <linux/pm_runtime.h><br>
<div>+#include <linux/clk.h><br>
+#include <linux/slab.h><br>
+#include <linux/io.h><br>
</div><div>+#include <linux/of_address.h><br>
+#include <linux/of_irq.h><br>
+#include <linux/of_i2c.h><br>
+<br>
+/*<br>
+ * HSI2C controller from Samsung supports 2 modes of operation<br>
+ * 1. Auto mode: Where in master automatically controls the whole transaction<br>
+ * 2. Manual mode: Software controls the transaction by issuing commands<br>
+ * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.<br>
+ *<br>
+ * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register<br>
+ *<br>
+ * Special bits are available for both modes of operation to set commands<br>
+ * and for checking transfer status<br>
+ */<br>
+<br>
</div>+/* Register Map */<br>
<div>+#define HSI2C_CTL 0x00<br>
+#define HSI2C_FIFO_CTL 0x04<br>
+#define HSI2C_TRAILIG_CTL 0x08<br>
+#define HSI2C_CLK_CTL 0x0C<br>
+#define HSI2C_CLK_SLOT 0x10<br>
+#define HSI2C_INT_ENABLE 0x20<br>
+#define HSI2C_INT_STATUS 0x24<br>
+#define HSI2C_ERR_STATUS 0x2C<br>
+#define HSI2C_FIFO_STATUS 0x30<br>
+#define HSI2C_TX_DATA 0x34<br>
+#define HSI2C_RX_DATA 0x38<br>
+#define HSI2C_CONF 0x40<br>
</div>+#define HSI2C_AUTO_CONF 0x44<br>
<div>+#define HSI2C_TIMEOUT 0x48<br>
+#define HSI2C_MANUAL_CMD 0x4C<br>
+#define HSI2C_TRANS_STATUS 0x50<br>
+#define HSI2C_TIMING_HS1 0x54<br>
+#define HSI2C_TIMING_HS2 0x58<br>
+#define HSI2C_TIMING_HS3 0x5C<br>
+#define HSI2C_TIMING_FS1 0x60<br>
+#define HSI2C_TIMING_FS2 0x64<br>
+#define HSI2C_TIMING_FS3 0x68<br>
+#define HSI2C_TIMING_SLA 0x6C<br>
+#define HSI2C_ADDR 0x70<br>
+<br>
</div>+/* I2C_CTL Register bits */<br>
<div>+#define HSI2C_FUNC_MODE_I2C (1u << 0)<br>
+#define HSI2C_MASTER (1u << 3)<br>
+#define HSI2C_RXCHON (1u << 6)<br>
+#define HSI2C_TXCHON (1u << 7)<br>
</div><div>+#define HSI2C_SW_RST (1u << 31)<br>
+<br>
</div>+/* I2C_FIFO_CTL Register bits */<br>
<div>+#define HSI2C_RXFIFO_EN (1u << 0)<br>
+#define HSI2C_TXFIFO_EN (1u << 1)<br>
</div><div>+#define HSI2C_FIFO_MAX (0x40)<br>
+#define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4)<br>
+#define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16)<br>
</div>+/* I2C_TRAILING_CTL Register bits */<br>
+#define HSI2C_TRAILING_COUNT (0xf)<br>
+<br>
+/* I2C_INT_EN Register bits */<br>
+#define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0)<br>
<div><div>+#define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1)<br>
+#define HSI2C_INT_TRAILING_EN (1u << 6)<br>
+#define HSI2C_INT_I2C_EN (1u << 9)<br>
+<br>
+/* I2C_INT_STAT Register bits */<br>
+#define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0)<br>
+#define HSI2C_INT_RX_ALMOSTFULL (1u << 1)<br>
+#define HSI2C_INT_TX_UNDERRUN (1u << 2)<br>
+#define HSI2C_INT_TX_OVERRUN (1u << 3)<br>
+#define HSI2C_INT_RX_UNDERRUN (1u << 4)<br>
+#define HSI2C_INT_RX_OVERRUN (1u << 5)<br>
+#define HSI2C_INT_TRAILING (1u << 6)<br>
+#define HSI2C_INT_I2C (1u << 9)<br>
+#define HSI2C_RX_INT (HSI2C_INT_RX_ALMOSTFULL | \<br>
+ HSI2C_INT_RX_UNDERRUN | \<br>
+ HSI2C_INT_RX_OVERRUN | \<br>
+ HSI2C_INT_TRAILING)<br>
+<br>
+/* I2C_FIFO_STAT Register bits */<br>
+#define HSI2C_RX_FIFO_EMPTY (1u << 24)<br>
+#define HSI2C_RX_FIFO_FULL (1u << 23)<br>
+#define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f)<br>
+#define HSI2C_TX_FIFO_EMPTY (1u << 8)<br>
+#define HSI2C_TX_FIFO_FULL (1u << 7)<br>
+#define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f)<br>
+#define HSI2C_FIFO_EMPTY (HSI2C_RX_FIFO_EMPTY | \<br>
+ HSI2C_TX_FIFO_EMPTY)<br>
+<br>
</div></div>+/* I2C_CONF Register bits */<br>
<div>+#define HSI2C_AUTO_MODE (1u << 31)<br>
+#define HSI2C_10BIT_ADDR_MODE (1u << 30)<br>
+#define HSI2C_HS_MODE (1u << 29)<br>
+<br>
</div>+/* I2C_AUTO_CONF Register bits */<br>
<div>+#define HSI2C_READ_WRITE (1u << 16)<br>
+#define HSI2C_STOP_AFTER_TRANS (1u << 17)<br>
+#define HSI2C_MASTER_RUN (1u << 31)<br>
+<br>
</div>+/* I2C_TIMEOUT Register bits */<br>
<div>+#define HSI2C_TIMEOUT_EN (1u << 31)<br>
+<br>
</div><div><div>+/* I2C_TRANS_STATUS register bits */<br>
+#define HSI2C_MASTER_BUSY (1u << 17)<br>
+#define HSI2C_SLAVE_BUSY (1u << 16)<br>
+#define HSI2C_TIMEOUT_AUTO (1u << 4)<br>
+#define HSI2C_NO_DEV (1u << 3)<br>
+#define HSI2C_NO_DEV_ACK (1u << 2)<br>
+#define HSI2C_TRANS_ABORT (1u << 1)<br>
+#define HSI2C_TRANS_DONE (1u << 0)<br>
+<br>
+/* I2C_ADDR register bits */<br>
+#define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0)<br>
+#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)<br>
+#define HSI2C_MASTER_ID(x) ((x & 0xff) << 24)<br>
+#define MASTER_ID(x) ((x & 0x7) + 0x08)<br>
+<br>
+/*<br>
+ * Controller operating frequency, timing values for operation<br>
+ * are calculated against this frequency<br>
+ */<br>
+#define HSI2C_HS_TX_CLOCK 1000000<br>
+#define HSI2C_FS_TX_CLOCK 1000000<br>
+#define HSI2C_HIGH_SPD 1<br>
+#define HSI2C_FAST_SPD 0<br>
+<br>
+#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))<br>
+<br>
+/* timeout for pm runtime autosuspend */<br>
+#define EXYNOS5_I2C_PM_TIMEOUT 1000 /* ms */<br>
+<br>
+struct exynos5_i2c {<br>
</div></div>+ struct i2c_adapter adap;<br>
<div>+ unsigned int suspended:1;<br>
+<br>
+ struct i2c_msg *msg;<br>
+ struct completion msg_complete;<br>
</div><div>+ unsigned int msg_ptr;<br>
+ unsigned int msg_len;<br>
</div><div>+<br>
+ unsigned int irq;<br>
+<br>
+ void __iomem *regs;<br>
+ struct clk *clk;<br>
+ struct device *dev;<br>
</div><div>+ int state;<br>
+<br>
+ /*<br>
+ * Since the TRANS_DONE bit is cleared on read, and we may read it<br>
+ * either during an IRQ or after a transaction, keep track of its<br>
+ * state here.<br>
+ */<br>
+ int trans_done;<br>
+<br>
+ /* Controller operating frequency */<br>
+ unsigned int fs_clock;<br>
+ unsigned int hs_clock;<br>
+<br>
+ /*<br>
+ * HSI2C Controller can operate in<br>
+ * 1. High speed upto 3.4Mbps<br>
+ * 2. Fast speed upto 1Mbps<br>
+ */<br>
+ int speed_mode;<br>
+ int bus_id;<br>
</div>+};<br>
+<br>
<div>+static const struct of_device_id exynos5_i2c_match[] = {<br>
</div>+ { .compatible = "samsung,exynos5-hsi2c" },<br>
<div>+ {},<br>
+};<br>
+MODULE_DEVICE_TABLE(of, exynos5_i2c_match);<br>
</div><div>+<br>
+static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)<br>
+{<br>
+ writel(readl(i2c->regs + HSI2C_INT_STATUS),<br>
</div>+ i2c->regs + HSI2C_INT_STATUS);<br>
+}<br>
+<br>
<div>+/*<br>
+ * exynos5_i2c_set_timing: updates the registers with appropriate<br>
+ * timing values calculated<br>
+ *<br>
+ * Returns 0 on success, -EINVAL if the cycle length cannot<br>
+ * be calculated.<br>
+ */<br>
+static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode)<br>
+{<br>
+ u32 i2c_timing_s1;<br>
+ u32 i2c_timing_s2;<br>
+ u32 i2c_timing_s3;<br>
+ u32 i2c_timing_sla;<br>
</div><div>+ unsigned int t_start_su, t_start_hd;<br>
+ unsigned int t_stop_su;<br>
+ unsigned int t_data_su, t_data_hd;<br>
+ unsigned int t_scl_l, t_scl_h;<br>
+ unsigned int t_sr_release;<br>
+ unsigned int t_ftl_cycle;<br>
</div><div>+ unsigned int clkin = clk_get_rate(i2c->clk);<br>
</div><div>+ unsigned int div, utemp0 = 0, utemp1 = 0, clk_cycle;<br>
+ unsigned int op_clk = (mode == HSI2C_HIGH_SPD) ?<br>
+ i2c->hs_clock : i2c->fs_clock;<br>
+<br>
+ /*<br>
</div>+ * FPCLK / FI2C =<br>
<div>+ * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE<br>
</div>+ * utemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)<br>
+ * utemp1 = (TSCLK_L + TSCLK_H + 2)<br>
<div>+ */<br>
+ t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;<br>
+ utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;<br>
+<br>
+ /* CLK_DIV max is 256 */<br>
</div><div>+ for (div = 0; div < 256; div++) {<br>
+ utemp1 = utemp0 / (div + 1);<br>
+<br>
+ /*<br>
+ * SCL_L and SCL_H each has max value of 255<br>
+ * Hence, For the clk_cycle to the have right value<br>
+ * utemp1 has to be less then 512 and more than 4.<br>
+ */<br>
+ if ((utemp1 < 512) && (utemp1 > 4)) {<br>
</div>+ clk_cycle = utemp1 - 2;<br>
+ break;<br>
<div>+ } else if (div == 255) {<br>
</div>+ dev_warn(i2c->dev, "Failed to calculate divisor");<br>
<div>+ return -EINVAL;<br>
+ }<br>
+ }<br>
</div>+<br>
+ t_scl_l = clk_cycle / 2;<br>
+ t_scl_h = clk_cycle / 2;<br>
<div>+ t_start_su = t_scl_l;<br>
+ t_start_hd = t_scl_l;<br>
+ t_stop_su = t_scl_l;<br>
+ t_data_su = t_scl_l / 2;<br>
+ t_data_hd = t_scl_l / 2;<br>
</div>+ t_sr_release = clk_cycle;<br>
<div>+<br>
+ i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;<br>
+ i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;<br>
</div>+ i2c_timing_s3 = div << 16 | t_sr_release << 0;<br>
<div>+ i2c_timing_sla = t_data_hd << 0;<br>
+<br>
+ dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",<br>
+ t_start_su, t_start_hd, t_stop_su);<br>
+ dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",<br>
+ t_data_su, t_scl_l, t_scl_h);<br>
+ dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",<br>
</div>+ div, t_sr_release);<br>
<div>+ dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);<br>
+<br>
</div>+ if (mode == HSI2C_HIGH_SPD) {<br>
<div>+ writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);<br>
+ writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);<br>
+ writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);<br>
+ } else {<br>
+ writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);<br>
+ writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);<br>
+ writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);<br>
+ }<br>
+ writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);<br>
+<br>
+ return 0;<br>
+}<br>
+<br>
</div><div>+static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)<br>
+{<br>
+ /*<br>
+ * Configure the Fast speed timing values<br>
+ * Even the High Speed mode initially starts with Fast mode<br>
+ */<br>
+ if (exynos5_i2c_set_timing(i2c, HSI2C_FAST_SPD)) {<br>
</div>+ dev_err(i2c->dev, "HSI2C FS Clock set up failed\n");<br>
<div>+ return -EINVAL;<br>
+ }<br>
+<br>
</div>+ /* configure the High speed timing values */<br>
<div>+ if (i2c->speed_mode == HSI2C_HIGH_SPD) {<br>
</div>+ if (exynos5_i2c_set_timing(i2c, HSI2C_HIGH_SPD)) {<br>
+ dev_err(i2c->dev, "HSI2C HS Clock set up failed\n");<br>
<div>+ return -EINVAL;<br>
+ }<br>
+ }<br>
</div><div>+<br>
+ return 0;<br>
+}<br>
+<br>
</div><div>+/*<br>
+ * exynos5_i2c_init: configures the controller for I2C functionality<br>
+ * Programs I2C controller for Master mode operation<br>
+ */<br>
</div>+static void exynos5_i2c_init(struct exynos5_i2c *i2c)<br>
+{<br>
+ u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);<br>
+<br>
+ writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),<br>
+ i2c->regs + HSI2C_CTL);<br>
+ writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);<br>
+<br>
<div>+ if (i2c->speed_mode == HSI2C_HIGH_SPD) {<br>
</div><div>+ writel(HSI2C_MASTER_ID(MASTER_ID(i2c->bus_id)),<br>
+ i2c->regs + HSI2C_ADDR);<br>
+ i2c_conf |= HSI2C_HS_MODE;<br>
+ }<br>
+<br>
</div>+ writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);<br>
+}<br>
+<br>
+static void exynos5_i2c_reset(struct exynos5_i2c *i2c)<br>
+{<br>
<div>+ u32 i2c_ctl;<br>
+<br>
+ /* Set and clear the bit for reset */<br>
+ i2c_ctl = readl(i2c->regs + HSI2C_CTL);<br>
+ i2c_ctl |= HSI2C_SW_RST;<br>
</div>+ writel(i2c_ctl, i2c->regs + HSI2C_CTL);<br>
+<br>
<div>+ i2c_ctl = readl(i2c->regs + HSI2C_CTL);<br>
+ i2c_ctl &= ~HSI2C_SW_RST;<br>
</div>+ writel(i2c_ctl, i2c->regs + HSI2C_CTL);<br>
+<br>
<div>+ /* We don't expect calculations to fail during the run */<br>
+ exynos5_hsi2c_clock_setup(i2c);<br>
+ /* Initialize the configure registers */<br>
+ exynos5_i2c_init(i2c);<br>
+}<br>
+<br>
+/*<br>
+ * exynos5_i2c_irq: top level IRQ servicing routine<br>
+ *<br>
+ * INT_STATUS registers gives the interrupt details. Further,<br>
+ * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed<br>
+ * state of the bus.<br>
+ */<br>
</div><div>+static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)<br>
+{<br>
+ struct exynos5_i2c *i2c = dev_id;<br>
</div><div>+ u32 fifo_level, int_status, fifo_status, trans_status;<br>
</div>+ unsigned char byte;<br>
<div>+ int len = 0;<br>
+<br>
+ i2c->state = -EINVAL;<br>
+<br>
</div>+ int_status = readl(i2c->regs + HSI2C_INT_STATUS);<br>
+ fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);<br>
+<br>
<div>+ if (int_status & HSI2C_INT_I2C) {<br>
</div><div>+ trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);<br>
</div><div><div>+ if (trans_status & HSI2C_NO_DEV_ACK) {<br>
+ dev_dbg(i2c->dev, "No ACK from device\n");<br>
+ i2c->state = -ENXIO;<br>
+ } else if (trans_status & HSI2C_NO_DEV) {<br>
+ dev_dbg(i2c->dev, "No device\n");<br>
+ i2c->state = -ENXIO;<br>
+ } else if (trans_status & HSI2C_TRANS_ABORT) {<br>
+ dev_dbg(i2c->dev, "Deal with arbitration lose\n");<br>
+ i2c->state = -EAGAIN;<br>
+ } else if (trans_status & HSI2C_TIMEOUT_AUTO) {<br>
+ dev_dbg(i2c->dev, "Accessing device timed out\n");<br>
+ i2c->state = -EAGAIN;<br>
+ } else if (trans_status & HSI2C_TRANS_DONE) {<br>
+ i2c->trans_done = 1;<br>
+ i2c->state = 0;<br>
+ }<br>
+ }<br>
+ /* TX_ALMOSTEMPTY can happen along with HSI2C_INT_I2C */<br>
+ else if (int_status &<br>
+ (HSI2C_INT_TX_UNDERRUN | HSI2C_INT_TX_ALMOSTEMPTY)) {<br>
+ fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);<br>
+<br>
+ /* To support probing the devices for detection */<br>
+ if (i2c->msg->len == 0) {<br>
+ i2c->state = -ENXIO;<br>
+ goto stop;<br>
+ }<br>
+<br>
+ len = HSI2C_FIFO_MAX - fifo_level;<br>
+ if (len > i2c->msg->len)<br>
</div></div>+ len = i2c->msg->len;<br>
+<br>
<div>+ i2c->msg_len += len;<br>
+ while (len > 0) {<br>
</div>+ byte = i2c->msg->buf[i2c->msg_ptr++];<br>
<div>+ writel(byte, i2c->regs + HSI2C_TX_DATA);<br>
</div><div>+ len--;<br>
+ }<br>
+ i2c->state = 0;<br>
+ goto stop;<br>
+ }<br>
+ /* If TX FIFO is full (give chance to clear) */<br>
+ else if (int_status & HSI2C_INT_TX_OVERRUN)<br>
</div>+ i2c->state = 0;<br>
+<br>
<div>+ if (int_status & (HSI2C_INT_RX_OVERRUN | HSI2C_INT_TRAILING |<br>
+ HSI2C_INT_RX_UNDERRUN | HSI2C_INT_RX_ALMOSTFULL)) {<br>
+ fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);<br>
+<br>
+ if (fifo_level >= i2c->msg->len)<br>
+ len = i2c->msg->len;<br>
+ else<br>
+ len = fifo_level;<br>
+<br>
+ i2c->msg_len += len;<br>
</div>+ while (len > 0) {<br>
<div>+ byte = (unsigned char)<br>
</div><div>+ readl(i2c->regs + HSI2C_RX_DATA);<br>
+ i2c->msg->buf[i2c->msg_ptr++] = byte;<br>
+ len--;<br>
+ }<br>
+ i2c->state = 0;<br>
+ }<br>
+<br>
+<br>
+ stop:<br>
+ if ((i2c->msg_len == i2c->msg->len) || (i2c->state < 0)) {<br>
</div><div>+ writel(0, i2c->regs + HSI2C_INT_ENABLE);<br>
</div><div>+ complete(&i2c->msg_complete);<br>
+ }<br>
+<br>
+ exynos5_i2c_clr_pend_irq(i2c);<br>
</div><div>+<br>
+ return IRQ_HANDLED;<br>
+}<br>
+<br>
</div><div>+/*<br>
+ * exynos5_i2c_wait_bus_idle<br>
+ *<br>
+ * Wait for the transaction to complete (indicated by the TRANS_DONE bit<br>
+ * being set), and, if this is the last message in a transfer, wait for the<br>
+ * MASTER_BUSY bit to be cleared.<br>
+ *<br>
+ * Returns -EBUSY if the bus cannot be bought to idle<br>
+ */<br>
</div>+static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c, int stop)<br>
+{<br>
<div>+ unsigned long stop_time;<br>
+ u32 trans_status;<br>
+<br>
+ /* wait for 100 milli seconds for the bus to be idle */<br>
+ stop_time = jiffies + msecs_to_jiffies(100) + 1;<br>
+ do {<br>
</div><div>+ trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);<br>
</div><div>+ if (trans_status & HSI2C_TRANS_DONE)<br>
+ i2c->trans_done = 1;<br>
+ /*<br>
+ * Only wait for MASTER_BUSY to be cleared if this is the last<br>
+ * message.<br>
+ */<br>
+ if ((!stop || !(trans_status & HSI2C_MASTER_BUSY)) &&<br>
+ i2c->trans_done)<br>
</div>+ return 0;<br>
+<br>
<div><div>+ usleep_range(50, 200);<br>
+ } while (time_before(jiffies, stop_time));<br>
+<br>
+ return -EBUSY;<br>
+}<br>
+<br>
+/*<br>
+ * exynos5_i2c_message_start: Configures the bus and starts the xfer<br>
+ * i2c: struct exynos5_i2c pointer for the current bus<br>
+ * stop: Enables stop after transfer if set. Set for last transfer of<br>
+ * in the list of messages.<br>
+ *<br>
+ * Configures the bus for read/write function<br>
+ * Sets chip address to talk to, message length to be sent.<br>
+ * Enables appropriate interrupts and sends start xfer command.<br>
+ */<br>
+static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)<br>
+{<br>
+ u32 i2c_ctl;<br>
+ u32 int_en = HSI2C_INT_I2C_EN;<br>
+ u32 i2c_auto_conf = 0;<br>
+ u32 fifo_ctl;<br>
+ u32 i2c_timeout;<br>
+<br>
+ /*<br>
+ * When the message length is > FIFO depth, set the FIFO trigger<br>
+ * at FIFO_MAX - 4. Just for ease of handling.<br>
+ */<br>
+ unsigned short len = (i2c->msg->len > HSI2C_FIFO_MAX) ?<br>
+ (HSI2C_FIFO_MAX - 4) : i2c->msg->len;<br>
</div></div><div>+<br>
+ /* Clear to enable Timeout */<br>
</div>+ i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);<br>
<div>+ i2c_timeout &= ~HSI2C_TIMEOUT_EN;<br>
+ writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);<br>
+<br>
</div><div>+ fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;<br>
</div>+ writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);<br>
+<br>
+ i2c_ctl = readl(i2c->regs + HSI2C_CTL);<br>
+ i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);<br>
<div>+ if (i2c->msg->flags & I2C_M_RD) {<br>
</div>+ i2c_ctl |= HSI2C_RXCHON;<br>
<div>+<br>
+ i2c_auto_conf |= HSI2C_READ_WRITE;<br>
+<br>
</div>+ fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(len);<br>
+ int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |<br>
+ HSI2C_INT_TRAILING_EN);<br>
+ } else {<br>
<div>+ i2c_ctl |= HSI2C_TXCHON;<br>
+<br>
+ fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(len);<br>
</div>+ int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;<br>
<div>+ }<br>
+<br>
+ if (stop == 1)<br>
+ i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;<br>
+<br>
</div>+ writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR);<br>
+<br>
+ writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);<br>
+ writel(i2c_ctl, i2c->regs + HSI2C_CTL);<br>
+<br>
<div>+ /* In auto mode the length of xfer cannot be 0 */<br>
+ if (i2c->msg->len == 0)<br>
+ i2c_auto_conf |= 0x1;<br>
+ else<br>
</div><div>+ i2c_auto_conf |= i2c->msg->len;<br>
+<br>
</div>+ writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);<br>
<div>+<br>
+ /* Start data transfer in Master mode */<br>
</div>+ i2c_auto_conf = readl(i2c->regs + HSI2C_AUTO_CONF);<br>
+ i2c_auto_conf |= HSI2C_MASTER_RUN;<br>
+ writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);<br>
+<br>
+ writel(int_en, i2c->regs + HSI2C_INT_ENABLE);<br>
+}<br>
+<br>
<div>+static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,<br>
</div>+ struct i2c_msg *msgs, int stop)<br>
<div>+{<br>
+ unsigned long timeout;<br>
</div>+ int ret;<br>
<div>+<br>
+ i2c->msg = msgs;<br>
</div><div>+ i2c->msg_ptr = 0;<br>
+ i2c->msg_len = 0;<br>
+ i2c->trans_done = 0;<br>
+<br>
+ INIT_COMPLETION(i2c->msg_complete);<br>
+<br>
+ exynos5_i2c_message_start(i2c, stop);<br>
+<br>
</div>+ ret = wait_for_completion_interruptible_timeout<br>
+ (&i2c->msg_complete, EXYNOS5_I2C_TIMEOUT);<br>
<div>+ if (ret >= 0)<br>
</div><div>+ timeout = ret;<br>
+ else<br>
</div>+ return ret;<br>
+<br>
<div>+ ret = i2c->state;<br>
+<br>
+ if ((timeout == 0) || (ret < 0)) {<br>
+ exynos5_i2c_reset(i2c);<br>
</div><div>+ if (timeout == 0) {<br>
</div><div>+ dev_warn(i2c->dev, "%s timeout\n",<br>
</div>+ (msgs->flags & I2C_M_RD) ? "rx" : "tx");<br>
+ return ret;<br>
+ } else if (ret == -EAGAIN) {<br>
<div>+ return ret;<br>
+ }<br>
+ }<br>
+<br>
</div><div>+ /*<br>
+ * If this is the last message to be transfered (stop == 1)<br>
+ * Then check if the bus can be brought back to idle.<br>
+ *<br>
+ * Return -EBUSY if the bus still busy.<br>
+ */<br>
+ if (exynos5_i2c_wait_bus_idle(i2c, stop))<br>
+ return -EBUSY;<br>
+<br>
+ /* Return the state as in interrupt routine */<br>
</div><div>+ return ret;<br>
+}<br>
+<br>
+static int exynos5_i2c_xfer(struct i2c_adapter *adap,<br>
+ struct i2c_msg *msgs, int num)<br>
+{<br>
+ struct exynos5_i2c *i2c = (struct exynos5_i2c *)adap->algo_data;<br>
</div><div>+ struct i2c_msg *msgs_ptr = msgs;<br>
</div><div>+ int retry, i = 0;<br>
+ int ret = 0, ret_pm;<br>
</div><div>+ int stop = 0;<br>
+<br>
</div><div>+ if (i2c->suspended) {<br>
+ dev_err(i2c->dev, "HS-I2C is not initialzed.\n");<br>
+ return -EIO;<br>
+ }<br>
+<br>
</div><div>+ ret_pm = pm_runtime_get_sync(i2c->dev);<br>
+ if (IS_ERR_VALUE(ret_pm)) {<br>
+ ret = -EIO;<br>
+ goto out;<br>
</div><div>+ }<br>
+<br>
+ clk_prepare_enable(i2c->clk);<br>
+<br>
+ for (retry = 0; retry < adap->retries; retry++) {<br>
+ for (i = 0; i < num; i++) {<br>
</div>+ stop = (i == num - 1);<br>
+<br>
+ ret = exynos5_i2c_xfer_msg(i2c, msgs_ptr, stop);<br>
<div>+ msgs_ptr++;<br>
+<br>
+ if (ret == -EAGAIN) {<br>
+ msgs_ptr = msgs;<br>
</div><div>+ break;<br>
+ } else if (ret < 0) {<br>
+ goto out;<br>
</div>+ }<br>
+ }<br>
+<br>
<div>+ if ((i == num) && (ret != -EAGAIN))<br>
+ break;<br>
</div><div>+<br>
+ dev_dbg(i2c->dev, "retrying transfer (%d)\n", retry);<br>
+<br>
+ udelay(100);<br>
+ }<br>
+<br>
</div><div>+ if (i == num) {<br>
</div><div>+ ret = num;<br>
+ } else {<br>
+ /* Only one message, cannot access the device */<br>
+ if (i == 1)<br>
+ ret = -EREMOTEIO;<br>
+ else<br>
+ ret = i;<br>
+<br>
+ dev_warn(i2c->dev, "xfer message failed\n");<br>
+ }<br>
+<br>
+ out:<br>
+ clk_disable_unprepare(i2c->clk);<br>
+ pm_runtime_mark_last_busy(i2c->dev);<br>
+ pm_runtime_put_autosuspend(i2c->dev);<br>
</div><div>+ return ret;<br>
+}<br>
+<br>
</div><div>+static u32 exynos5_i2c_func(struct i2c_adapter *adap)<br>
+{<br>
</div>+ return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);<br>
<div>+}<br>
+<br>
+static const struct i2c_algorithm exynos5_i2c_algorithm = {<br>
+ .master_xfer = exynos5_i2c_xfer,<br>
+ .functionality = exynos5_i2c_func,<br>
+};<br>
+<br>
</div><div>+static int exynos5_i2c_probe(struct platform_device *pdev)<br>
+{<br>
</div>+ struct device_node *np = pdev->dev.of_node;<br>
+ struct exynos5_i2c *i2c;<br>
+ struct resource *mem;<br>
+ int ret;<br>
+<br>
+ if (!np) {<br>
<div>+ dev_err(&pdev->dev, "no device node\n");<br>
+ return -ENOENT;<br>
+ }<br>
+<br>
</div><div>+ i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);<br>
+ if (!i2c) {<br>
+ dev_err(&pdev->dev, "no memory for state\n");<br>
+ return -ENOMEM;<br>
+ }<br>
+<br>
</div>+ /* Mode of operation High/Fast Speed mode */<br>
<div>+ if (of_get_property(np, "samsung,hs-mode", NULL)) {<br>
+ i2c->speed_mode = HSI2C_HIGH_SPD;<br>
+ i2c->fs_clock = HSI2C_FS_TX_CLOCK;<br>
+ if (of_property_read_u32(np, "clock-frequency", &i2c->hs_clock))<br>
+ i2c->hs_clock = HSI2C_HS_TX_CLOCK;<br>
+ } else {<br>
+ i2c->speed_mode = HSI2C_FAST_SPD;<br>
+ if (of_property_read_u32(np, "clock-frequency", &i2c->fs_clock))<br>
+ i2c->fs_clock = HSI2C_FS_TX_CLOCK;<br>
</div>+ }<br>
+<br>
+ strlcpy(i2c-><a href="http://adap.name" target="_blank">adap.name</a>, "exynos5-i2c", sizeof(i2c-><a href="http://adap.name" target="_blank">adap.name</a>));<br>
<div>+ i2c->adap.owner = THIS_MODULE;<br>
+ i2c->adap.algo = &exynos5_i2c_algorithm;<br>
+ i2c->adap.retries = 2;<br>
+ i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;<br>
+<br>
+ i2c->dev = &pdev->dev;<br>
</div>+ i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");<br>
<div>+ if (IS_ERR(i2c->clk)) {<br>
+ dev_err(&pdev->dev, "cannot get clock\n");<br>
</div><div>+ return -ENOENT;<br>
+ }<br>
+<br>
</div>+ clk_prepare_enable(i2c->clk);<br>
+<br>
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);<br>
+ i2c->regs = devm_ioremap_resource(&pdev->dev, mem);<br>
+ if (IS_ERR(i2c->regs)) {<br>
<div>+ dev_err(&pdev->dev, "cannot map HS-I2C IO\n");<br>
</div>+ ret = PTR_ERR(i2c->regs);<br>
<div>+ goto err_clk;<br>
+ }<br>
+<br>
</div>+ i2c->adap.dev.of_node = np;<br>
<div>+ i2c->adap.algo_data = i2c;<br>
+ i2c->adap.dev.parent = &pdev->dev;<br>
+<br>
</div><div>+ /* Clear pending interrupts from u-boot or misc causes */<br>
+ exynos5_i2c_clr_pend_irq(i2c);<br>
</div><div>+<br>
+ init_completion(&i2c->msg_complete);<br>
+<br>
</div>+ i2c->irq = ret = irq_of_parse_and_map(np, 0);<br>
<div>+ if (ret <= 0) {<br>
+ dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");<br>
</div>+ ret = -EINVAL;<br>
<div>+ goto err_clk;<br>
+ }<br>
+<br>
</div><div>+ ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,<br>
</div>+ 0, dev_name(&pdev->dev), i2c);<br>
<div>+<br>
+ if (ret != 0) {<br>
+ dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);<br>
</div><div>+ goto err_clk;<br>
+ }<br>
+<br>
+ /*<br>
+ * TODO: Use private lock to avoid race conditions as<br>
+ * mentioned in pm_runtime.txt<br>
+ */<br>
+ pm_runtime_enable(i2c->dev);<br>
+ pm_runtime_set_autosuspend_delay(i2c->dev, EXYNOS5_I2C_PM_TIMEOUT);<br>
+ pm_runtime_use_autosuspend(i2c->dev);<br>
+<br>
+ ret = pm_runtime_get_sync(i2c->dev);<br>
+ if (IS_ERR_VALUE(ret))<br>
</div>+ goto err_clk;<br>
+<br>
<div>+ ret = exynos5_hsi2c_clock_setup(i2c);<br>
+ if (ret)<br>
+ goto err_pm;<br>
+<br>
+ i2c->bus_id = of_alias_get_id(i2c->adap.dev.of_node, "hsi2c");<br>
+<br>
+ exynos5_i2c_init(i2c);<br>
</div>+<br>
+ i2c-><a href="http://adap.nr" target="_blank">adap.nr</a> = -1;<br>
<div>+ ret = i2c_add_numbered_adapter(&i2c->adap);<br>
+ if (ret < 0) {<br>
+ dev_err(&pdev->dev, "failed to add bus to i2c core\n");<br>
</div>+ goto err_pm;<br>
<div>+ }<br>
+<br>
+ of_i2c_register_devices(&i2c->adap);<br>
+ platform_set_drvdata(pdev, i2c);<br>
+<br>
</div><div>+ clk_disable_unprepare(i2c->clk);<br>
+ pm_runtime_mark_last_busy(i2c->dev);<br>
+ pm_runtime_put_autosuspend(i2c->dev);<br>
</div><div>+<br>
+ return 0;<br>
+<br>
</div><div>+ err_pm:<br>
+ pm_runtime_put(i2c->dev);<br>
+ pm_runtime_disable(&pdev->dev);<br>
</div><div>+ err_clk:<br>
+ clk_disable_unprepare(i2c->clk);<br>
</div><div>+ return ret;<br>
+}<br>
+<br>
+static int exynos5_i2c_remove(struct platform_device *pdev)<br>
+{<br>
+ struct exynos5_i2c *i2c = platform_get_drvdata(pdev);<br>
</div><div>+ int ret;<br>
+<br>
+ ret = pm_runtime_get_sync(&pdev->dev);<br>
+ if (IS_ERR_VALUE(ret))<br>
</div>+ return ret;<br>
+<br>
<div>+ i2c_del_adapter(&i2c->adap);<br>
+<br>
+ pm_runtime_put(&pdev->dev);<br>
+ pm_runtime_disable(&pdev->dev);<br>
</div><div>+<br>
+ clk_disable_unprepare(i2c->clk);<br>
+<br>
</div><div>+ return 0;<br>
+}<br>
+<br>
+#ifdef CONFIG_PM<br>
+static int exynos5_i2c_suspend_noirq(struct device *dev)<br>
+{<br>
+ struct platform_device *pdev = to_platform_device(dev);<br>
+ struct exynos5_i2c *i2c = platform_get_drvdata(pdev);<br>
+<br>
</div><div>+ i2c->suspended = 1;<br>
+<br>
</div><div>+ return 0;<br>
+}<br>
+<br>
</div>+static int exynos5_i2c_resume_noirq(struct device *dev)<br>
<div>+{<br>
+ struct platform_device *pdev = to_platform_device(dev);<br>
+ struct exynos5_i2c *i2c = platform_get_drvdata(pdev);<br>
</div><div>+ int ret = 0;<br>
+<br>
</div>+ clk_prepare_enable(i2c->clk);<br>
+<br>
+ ret = exynos5_hsi2c_clock_setup(i2c);<br>
+ if (ret) {<br>
+ clk_disable_unprepare(i2c->clk);<br>
+ return ret;<br>
+ }<br>
<div>+<br>
+ exynos5_i2c_init(i2c);<br>
+ clk_disable_unprepare(i2c->clk);<br>
+ i2c->suspended = 0;<br>
+<br>
</div><div>+ return 0;<br>
+}<br>
+<br>
+static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {<br>
+ .suspend_noirq = exynos5_i2c_suspend_noirq,<br>
</div>+ .resume_noirq = exynos5_i2c_resume_noirq,<br>
<div>+};<br>
+<br>
+#define EXYNOS5_DEV_PM_OPS (&exynos5_i2c_dev_pm_ops)<br>
+#else<br>
+#define EXYNOS5_DEV_PM_OPS NULL<br>
+#endif<br>
+<br>
+static struct platform_driver exynos5_i2c_driver = {<br>
+ .probe = exynos5_i2c_probe,<br>
+ .remove = exynos5_i2c_remove,<br>
</div><div>+ .driver = {<br>
+ .owner = THIS_MODULE,<br>
</div>+ .name = "exynos5-hsi2c",<br>
+ .pm = EXYNOS5_DEV_PM_OPS,<br>
+ .of_match_table = exynos5_i2c_match,<br>
<div>+ },<br>
+};<br>
+<br>
+static int __init i2c_adap_exynos5_init(void)<br>
+{<br>
+ return platform_driver_register(&exynos5_i2c_driver);<br>
+}<br>
+subsys_initcall(i2c_adap_exynos5_init);<br>
+<br>
+static void __exit i2c_adap_exynos5_exit(void)<br>
+{<br>
+ platform_driver_unregister(&exynos5_i2c_driver);<br>
+}<br>
+module_exit(i2c_adap_exynos5_exit);<br>
+<br>
+MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");<br>
</div>+MODULE_AUTHOR("Naveen Krishna Chatradhi, <<a href="mailto:ch.naveen@samsung.com" target="_blank">ch.naveen@samsung.com</a>>");<br>
<div>+MODULE_AUTHOR("Taekgyun Ko, <<a href="mailto:taeggyun.ko@samsung.com" target="_blank">taeggyun.ko@samsung.com</a>>");<br>
</div>+MODULE_LICENSE("GPL v2");<br>
<span><font color="#888888">--<br>
1.7.9.5<br>
<br>
</font></span></blockquote></div><br><br clear="all"><div><br></div>-- <br>Shine bright,<br>(: Nav :)