<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Wed, Apr 10, 2013 at 4:48 PM, Michal Bachraty <span dir="ltr"><<a href="mailto:michal.bachraty@streamunlimited.com" target="_blank">michal.bachraty@streamunlimited.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Sebastian,<br>
This driver doesn't work for me. In my case, u-boot initializes si-5351 and<br>
power down unused clocks while booting kernel. there is need for power up<br>
clocks as was in previous versions of your driver.<br>
See patch, whre the problem is fixed:<br>
<br>
@@ -992,6 +992,10 @@ static long si5351_clkout_round_rate(struct clk_hw *hw,<br>
unsigned long rate,<br>
} while (1);<br>
<div class="im"> }<br>
rate = *parent_rate >> rdiv;<br>
+<br>
</div>+ /* powerup clkout */<br>
<div class="im">+ si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,<br>
+ SI5351_CLK_POWERDOWN, 0);<br>
<br>
</div> dev_dbg(&hwdata->drvdata->client->dev,<br>
<div class="im"> "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",<br>
<br>
</div>With this lines, driver works well.<br></blockquote><div><br></div><div>Hmm, is there any driver using the clock output? Does it clk_prepare_enable() the clock?<br></div><div>I tend not to mess with anything the bootloader or eeprom config left disabled. It works<br>
for me, but here the driver will prepare/enable the clock prior use.<br></div><div> <br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Also,<br>
<div><div class="h5"><br>
> > +==Example==<br>
> > +<br>
> > +/* 25MHz reference crystal */<br>
> > +ref25: ref25M {<br>
> > + compatible = "fixed-clock";<br>
> > + #clock-cells = <0>;<br>
> > + clock-frequency = <25000000>;<br>
> > +};<br>
> > +<br>
> > +i2c-master-node {<br>
> > +<br>
> > + /* Si5351a msop10 i2c clock generator */<br>
> > + si5351a: clock-generator@60 {<br>
> > + compatible = "silabs,si5351a-msop";<br>
> > + reg = <0x60>;<br>
> > + #address-cells = <1>;<br>
> > + #size-cells = <0>;<br>
> > + #clock-cells = <1>;<br>
> > +<br>
> > + /* connect xtal input to 25MHz reference */<br>
> > + clocks = <&ref25>;<br>
> > +<br>
> > + /* connect xtal input as source of pll0 and pll1 */<br>
> > + silabs,pll-source = <0 0>, <1 0>;<br>
> > +<br>
> > + /*<br>
> > + * overwrite clkout0 configuration with:<br>
> > + * - 8mA output drive strength<br>
> > + * - pll0 as clock source of multisynth0<br>
> > + * - multisynth0 as clock source of output divider<br>
> > + * - multisynth0 can change pll0<br>
> > + * - set initial clock frequency of 74.25MHz<br>
> > + */<br>
> > + clkout0 {<br>
> > + reg = <0>;<br>
> > + silabs,drive-strength = <8>;<br>
> > + silabs,multisynth-source = <0>;<br>
> > + silabs,clock-source = <0>;<br>
> > + silabs,pll-master;<br>
> > + clock-frequency = <74250000>;<br>
> > + };<br>
> > +<br>
> > + /*<br>
> > + * overwrite clkout1 configuration with:<br>
> > + * - 4mA output drive strength<br>
> > + * - pll1 as clock source of multisynth1<br>
> > + * - multisynth1 as clock source of output divider<br>
> > + * - multisynth1 can change pll1<br>
> > + */<br>
> > + clkout1 {<br>
> > + reg = <1>;<br>
> > + silabs,drive-strength = <4>;<br>
> > + silabs,multisynth-source = <1>;<br>
> > + silabs,clock-source = <0>;<br>
> > + pll-master;<br>
> > + };<br>
> > +<br>
</div></div> Is definition of pll-master in clkout1 correct? should not be silabs,pll-<br>
master ?<br></blockquote></div><br></div><div class="gmail_extra">Good catch.<br><br>Sebastian<br></div></div>