<div dir="ltr">Hi Naveen,<div class="gmail_extra"><br><div class="gmail_quote">On Mon, Mar 11, 2013 at 9:32 PM, Naveen Krishna Chatradhi <span dir="ltr"><<a href="mailto:ch.naveen@samsung.com" target="_blank">ch.naveen@samsung.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div class="im">Adds support for High Speed I2C driver found in Exynos5 and later<br>
SoCs from Samsung. This driver currently supports Auto mode.<br>
<br>
Driver only supports Device Tree method.<br>
</div><div class="im">Note: Added debugfs support for registers view, not tested.<br>
<br>
</div><div class="im">Signed-off-by: Taekgyun Ko <<a href="mailto:taeggyun.ko@samsung.com">taeggyun.ko@samsung.com</a>><br>
Signed-off-by: Naveen Krishna Chatradhi <<a href="mailto:ch.naveen@samsung.com">ch.naveen@samsung.com</a>><br>
</div>Cc: R. Chandrasekar <<a href="mailto:rcsekar@samsung.com">rcsekar@samsung.com</a>><br>
---<br>
Changes since v3: <a href="http://lkml.org/lkml/2012/12/28/46" target="_blank">http://lkml.org/lkml/2012/12/28/46</a><br>
1. Added Documentation for DT bindings<br>
2. Removed the bus_num, as Doug's pick id from DT is merged in i2c/for-next<br>
3. Split the xfer function for better clarity.<br>
4. Streamlined code flow in isr, handled trans_status register in xfer_msg call.<br>
<br>
.../devicetree/bindings/i2c/i2c-exynos5.txt | 50 ++<br>
<div class="im"> drivers/i2c/busses/Kconfig | 7 +<br>
drivers/i2c/busses/Makefile | 1 +<br>
</div> drivers/i2c/busses/i2c-exynos5.c | 743 ++++++++++++++++++++<br>
4 files changed, 801 insertions(+)<br>
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-exynos5.txt<br>
create mode 100644 drivers/i2c/busses/i2c-exynos5.c<br>
<br>
diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt<br>
new file mode 100644<br>
index 0000000..0bc9347<br>
--- /dev/null<br>
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt<br>
@@ -0,0 +1,50 @@<br>
+* Samsung's High Speed I2C controller<br>
+<br>
+The Samsung's High Speed I2C controller is used to interface with I2C devices<br>
+at various speeds ranging from 100khz to 3.4Mhz.<br>
+<br>
+Required properties:<br>
+ - compatible: value should be.<br>
+ (a) "samsung,exynos5-hsi2c", for i2c compatible with exynos5 hsi2c.<br>
+ - reg: physical base address of the controller and length of memory mapped<br>
+ region.<br>
+ - interrupts: interrupt number to the cpu.<br>
+<br>
+ - Samsung GPIO variant (deprecated):<br>
+ - gpios: The order of the gpios should be the following: <SDA, SCL>.<br>
+ The gpio specifier depends on the gpio controller.<br>
+ - Pinctrl variant (preferred, if available):<br>
+ - pinctrl-0: Pin control group to be used for this controller.<br>
+ - pinctrl-names: Should contain only one value - "default".<br>
+<br>
+Optional properties:<br>
+ - samsung,hs-mode: Mode of operation, High speed or Fast speed mode. If not<br>
+ specified, default value is 0.<br>
+ - samsung,hs-clock-freq: Desired operating frequency in Hz of the bus.<br>
+ If not specified, the default value in Hz is 100000.<br>
+ - samsung,fs-clock-freq: Desired operarting frequency in Hz of the bus.<br>
+ If not specified, the default value in Hz is 100000.<br>
+<br>
+Example:<br>
+<br>
+ hsi2c@12ca0000 {<br>
+ compatible = "samsung,exynos5-hsi2c";<br>
+ reg = <0x12ca0000 0x100>;<br>
+ interrupts = <56>;<br>
+ samsung,fs-clock-freq = <100000>;<br>
+ /* Samsung GPIO variant begins here */<br>
+ gpios = <&gpd1 2 0 /* SDA */<br>
+ &gpd1 3 0 /* SCL */>;<br>
+ /* Samsung GPIO variant ends here */<br>
+ /* Pinctrl variant begins here */<br>
+ pinctrl-0 = <&i2c4_bus>;<br>
+ pinctrl-names = "default";<br>
+ /* Pinctrl variant ends here */<br>
+ #address-cells = <1>;<br>
+ #size-cells = <0>;<br>
+<br>
+ s2mps11_pmic@66 {<br>
+ compatible = "samsung,s2mps11-pmic";<br>
+ reg = <0x66>;<br>
+ };<br>
+ };<br>
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig<br>
index a3725de..78b4936 100644<br>
--- a/drivers/i2c/busses/Kconfig<br>
+++ b/drivers/i2c/busses/Kconfig<br>
@@ -434,6 +434,13 @@ config I2C_EG20T<br>
ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.<br>
ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.<br>
<br>
+config I2C_EXYNOS5<br>
<div class="im">+ tristate "Exynos5 high-speed I2C driver"<br>
</div>+ depends on ARCH_EXYNOS5 && OF<br>
+ help<br>
<div class="im">+ Say Y here to include support for High-speed I2C controller in the<br>
+ Exynos5 based Samsung SoCs.<br>
+<br>
</div> config I2C_GPIO<br>
tristate "GPIO-based bitbanging I2C"<br>
depends on GENERIC_GPIO<br>
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile<br>
index 8f4fc23..b19366c 100644<br>
--- a/drivers/i2c/busses/Makefile<br>
+++ b/drivers/i2c/busses/Makefile<br>
@@ -42,6 +42,7 @@ i2c-designware-platform-objs := i2c-designware-platdrv.o<br>
obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o<br>
i2c-designware-pci-objs := i2c-designware-pcidrv.o<br>
obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o<br>
+obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o<br>
obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o<br>
obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o<br>
obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o<br>
<div class="im">diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c<br>
new file mode 100644<br>
</div>index 0000000..fe30b0b<br>
--- /dev/null<br>
+++ b/drivers/i2c/busses/i2c-exynos5.c<br>
@@ -0,0 +1,743 @@<br>
<div class="im">+/**<br>
+ * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver<br>
</div>+ *<br>
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.<br>
+ *<br>
<div class="im">+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License version 2 as<br>
+ * published by the Free Software Foundation.<br>
+*/<br>
+<br>
+#include <linux/kernel.h><br>
+#include <linux/module.h><br>
</div>+#include <linux/debugfs.h><br>
<div class="im">+<br>
+#include <linux/i2c.h><br>
+#include <linux/init.h><br>
+#include <linux/time.h><br>
+#include <linux/interrupt.h><br>
+#include <linux/delay.h><br>
+#include <linux/errno.h><br>
+#include <linux/err.h><br>
+#include <linux/platform_device.h><br>
</div>+#include <linux/pm_runtime.h><br>
<div class="im">+#include <linux/clk.h><br>
+#include <linux/slab.h><br>
+#include <linux/io.h><br>
</div><div class="im">+#include <linux/of_address.h><br>
+#include <linux/of_gpio.h><br>
+#include <linux/of_irq.h><br>
+#include <linux/of_i2c.h><br>
+<br>
</div>+/* Register Map */<br>
<div class="im">+#define HSI2C_CTL 0x00<br>
+#define HSI2C_FIFO_CTL 0x04<br>
+#define HSI2C_TRAILIG_CTL 0x08<br>
+#define HSI2C_CLK_CTL 0x0C<br>
+#define HSI2C_CLK_SLOT 0x10<br>
+#define HSI2C_INT_ENABLE 0x20<br>
+#define HSI2C_INT_STATUS 0x24<br>
+#define HSI2C_ERR_STATUS 0x2C<br>
+#define HSI2C_FIFO_STATUS 0x30<br>
+#define HSI2C_TX_DATA 0x34<br>
+#define HSI2C_RX_DATA 0x38<br>
+#define HSI2C_CONF 0x40<br>
</div>+#define HSI2C_AUTO_CONF 0x44<br>
<div class="im">+#define HSI2C_TIMEOUT 0x48<br>
+#define HSI2C_MANUAL_CMD 0x4C<br>
+#define HSI2C_TRANS_STATUS 0x50<br>
+#define HSI2C_TIMING_HS1 0x54<br>
+#define HSI2C_TIMING_HS2 0x58<br>
+#define HSI2C_TIMING_HS3 0x5C<br>
+#define HSI2C_TIMING_FS1 0x60<br>
+#define HSI2C_TIMING_FS2 0x64<br>
+#define HSI2C_TIMING_FS3 0x68<br>
+#define HSI2C_TIMING_SLA 0x6C<br>
+#define HSI2C_ADDR 0x70<br>
+<br>
</div>+/* I2C_CTL Register bits */<br>
<div class="im">+#define HSI2C_FUNC_MODE_I2C (1u << 0)<br>
+#define HSI2C_MASTER (1u << 3)<br>
+#define HSI2C_RXCHON (1u << 6)<br>
+#define HSI2C_TXCHON (1u << 7)<br>
</div><div class="im">+#define HSI2C_SW_RST (1u << 31)<br>
+<br>
</div>+/* I2C_FIFO_CTL Register bits */<br>
<div class="im">+#define HSI2C_RXFIFO_EN (1u << 0)<br>
+#define HSI2C_TXFIFO_EN (1u << 1)<br>
+#define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16)<br>
+#define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4)<br>
+<br>
</div>+/* I2C_TRAILING_CTL Register bits */<br>
+#define HSI2C_TRAILING_COUNT (0xf)<br>
+<br>
+/* I2C_INT_EN Register bits */<br>
+#define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0)<br>
<div class="im">+#define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1)<br>
+#define HSI2C_INT_TRAILING_EN (1u << 6)<br>
+#define HSI2C_INT_I2C_EN (1u << 9)<br>
+<br>
+/* I2C_FIFO_STAT Register bits */<br>
</div>+#define HSI2C_RX_FIFO_EMPTY (1u << 24)<br>
+#define HSI2C_RX_FIFO_FULL (1u << 23)<br>
<div class="im">+#define HSI2C_TX_FIFO_EMPTY (1u << 8)<br>
+#define HSI2C_TX_FIFO_FULL (1u << 7)<br>
+<br>
</div>+#define HSI2C_RX_FIFO_EMPTY (1u << 24)<br>
+#define HSI2C_FIFO_EMPTY (HSI2C_RX_FIFO_EMPTY | \<br>
+ HSI2C_TX_FIFO_EMPTY)<br>
+<br>
+/* I2C_CONF Register bits */<br>
<div class="im">+#define HSI2C_AUTO_MODE (1u << 31)<br>
+#define HSI2C_10BIT_ADDR_MODE (1u << 30)<br>
+#define HSI2C_HS_MODE (1u << 29)<br>
+<br>
</div>+/* I2C_AUTO_CONF Register bits */<br>
<div class="im">+#define HSI2C_READ_WRITE (1u << 16)<br>
+#define HSI2C_STOP_AFTER_TRANS (1u << 17)<br>
+#define HSI2C_MASTER_RUN (1u << 31)<br>
+<br>
</div>+/* I2C_TIMEOUT Register bits */<br>
<div class="im">+#define HSI2C_TIMEOUT_EN (1u << 31)<br>
+<br>
</div><div class="im">+/* I2C_TRANS_STATUS register bits */<br>
</div>+#define HSI2C_MASTER_BUSY (1u << 17)<br>
+#define HSI2C_SLAVE_BUSY (1u << 16)<br>
+#define HSI2C_NO_DEV (1u << 3)<br>
+#define HSI2C_NO_DEV_ACK (1u << 2)<br>
<div class="im">+#define HSI2C_TRANS_ABORT (1u << 1)<br>
+#define HSI2C_TRANS_DONE (1u << 0)<br>
</div><div class="im">+<br>
+/* I2C_ADDR register bits */<br>
+#define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0)<br>
+#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)<br>
+#define HSI2C_MASTER_ID(x) ((x & 0xff) << 24)<br>
+<br>
</div>+/* Controller operating frequency, timing values for operation<br>
+ * are calculated against this frequency<br>
+ */<br>
+#define HSI2C_HS_TX_CLOCK 1000000<br>
+#define HSI2C_FS_TX_CLOCK 1000000<br>
<div class="im">+#define HSI2C_HIGH_SPD 1<br>
+#define HSI2C_FAST_SPD 0<br>
+<br>
+#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))<br>
+<br>
+/* timeout for pm runtime autosuspend */<br>
+#define EXYNOS5_I2C_PM_TIMEOUT 1000 /* ms */<br>
+<br>
+struct exynos5_i2c {<br>
</div>+ struct i2c_adapter adap;<br>
<div class="im">+ unsigned int suspended:1;<br>
+<br>
+ struct i2c_msg *msg;<br>
+ struct completion msg_complete;<br>
</div>+ unsigned int msg_ptr;<br>
<div class="im">+<br>
+ unsigned int irq;<br>
+<br>
+ void __iomem *regs;<br>
+ struct clk *clk;<br>
+ struct device *dev;<br>
+<br>
</div>+ /* GPIO lines for SDA/SCL*/<br>
<div class="im">+ int gpios[2];<br>
+<br>
</div>+ /* Controller operating frequency */<br>
<div class="im">+ unsigned int clock;<br>
+<br>
</div>+ /* HSI2C Controller can operate in<br>
+ * 1. High speed upto 3.4Mbps<br>
+ * 2. Fast speed upto 1Mbps<br>
+ */<br>
+ int speed_mode;<br>
+};<br>
+<br>
<div class="im">+static const struct of_device_id exynos5_i2c_match[] = {<br>
</div>+ { .compatible = "samsung,exynos5-hsi2c" },<br>
<div class="im">+ {},<br>
+};<br>
+MODULE_DEVICE_TABLE(of, exynos5_i2c_match);<br>
</div><div class="im">+<br>
+static inline void exynos5_i2c_stop(struct exynos5_i2c *i2c)<br>
+{<br>
+ writel(0, i2c->regs + HSI2C_INT_ENABLE);<br>
+<br>
+ complete(&i2c->msg_complete);<br>
+}<br>
+<br>
</div><div class="im">+static void exynos5_i2c_en_timeout(struct exynos5_i2c *i2c)<br>
+{<br>
</div>+ u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);<br>
<div class="im">+<br>
+ /* Clear to enable Timeout */<br>
+ i2c_timeout &= ~HSI2C_TIMEOUT_EN;<br>
+ writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);<br>
+}<br>
+<br>
</div><div class="im">+static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c)<br>
+{<br>
</div>+ u32 i2c_timing_s1;<br>
+ u32 i2c_timing_s2;<br>
+ u32 i2c_timing_s3;<br>
+ u32 i2c_timing_sla;<br>
+ unsigned int op_clk = i2c->clock;<br>
<div class="im">+ unsigned int clkin = clk_get_rate(i2c->clk);<br>
+ unsigned int n_clkdiv;<br>
+ unsigned int t_start_su, t_start_hd;<br>
+ unsigned int t_stop_su;<br>
+ unsigned int t_data_su, t_data_hd;<br>
+ unsigned int t_scl_l, t_scl_h;<br>
+ unsigned int t_sr_release;<br>
+ unsigned int t_ftl_cycle;<br>
+ unsigned int i = 0, utemp0 = 0, utemp1 = 0, utemp2 = 0;<br></div></blockquote><div><br></div><div style>Can you think of a better name for utemp0 and utemp2? Is utemp2 a clock divisor?</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<div class="im">
+<br>
</div><div><div class="h5">+ /* FPCLK / FI2C =<br>
+ * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE<br>
+ * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)<br>
+ * uTemp1 = (TSCLK_L + TSCLK_H + 2)<br>
+ * uTemp2 = TSCLK_L + TSCLK_H<br>
+ */<br>
+ t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;<br>
+ utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;<br>
+<br>
+ /* CLK_DIV max is 256 */<br>
+ for (i = 0; i < 256; i++) {<br>
+ utemp1 = utemp0 / (i + 1);<br>
+ /* SCLK_L/H max is 256 / 2 */<br>
+ if (utemp1 < 128) {<br>
+ utemp2 = utemp1 - 2;<br>
+ break;<br>
+ }<br></div></div></blockquote><div><br></div><div style>I suppose this loop can't exit until i is at least utemp / 128, so perhaps could start the loop at that value? This code seems to be on the noirq resume path, so should be fast if possible.</div>
<div style><br></div><div style>What happens if i gets to 256? Is that an error, since in that case utemp2 is not set?</div><div style><br></div><div style>Also could consider moving this loop into a function.</div><div style>
<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div><div class="h5">
+ }<span style="color:rgb(34,34,34)"> </span></div></div></blockquote><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<div><div class="h5">
+<br>
+ n_clkdiv = i;<br>
+ t_scl_l = utemp2 / 2;<br>
+ t_scl_h = utemp2 / 2;<br>
+ t_start_su = t_scl_l;<br>
+ t_start_hd = t_scl_l;<br>
+ t_stop_su = t_scl_l;<br>
+ t_data_su = t_scl_l / 2;<br>
+ t_data_hd = t_scl_l / 2;<br>
+ t_sr_release = utemp2;<br>
+<br>
+ i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;<br>
+ i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;<br>
+ i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;<br>
+ i2c_timing_sla = t_data_hd << 0;<br>
+<br>
+ dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",<br>
+ t_start_su, t_start_hd, t_stop_su);<br>
+ dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",<br>
+ t_data_su, t_scl_l, t_scl_h);<br>
+ dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",<br>
+ n_clkdiv, t_sr_release);<br>
+ dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);<br>
+<br>
+ if (i2c->speed_mode == HSI2C_HIGH_SPD) {<br>
+ writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);<br>
+ writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);<br>
+ writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);<br>
+ } else {<br>
+ writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);<br>
+ writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);<br>
+ writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);<br>
+ }<br>
+ writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);<br>
+<br>
+ return 0;<br>
+}<br>
+<br>
</div></div>+static void exynos5_i2c_init(struct exynos5_i2c *i2c)<br>
+{<br>
+ u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);<br>
+<br>
+ writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),<br>
+ i2c->regs + HSI2C_CTL);<br>
+ writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);<br>
<div class="im">+<br>
+ exynos5_i2c_set_timing(i2c);<br>
+<br>
+ if (i2c->speed_mode == HSI2C_HIGH_SPD)<br>
+ i2c_conf |= HSI2C_HS_MODE;<br>
+<br>
</div>+ writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);<br>
+}<br>
+<br>
+static void exynos5_i2c_reset(struct exynos5_i2c *i2c)<br>
+{<br>
+ u32 i2c_ctl;<br>
+<br>
+ /* Set and clear the bit for reset */<br>
+ i2c_ctl = readl(i2c->regs + HSI2C_CTL);<br>
+ i2c_ctl |= HSI2C_SW_RST;<br>
+ writel(i2c_ctl, i2c->regs + HSI2C_CTL);<br>
+<br>
+ i2c_ctl = readl(i2c->regs + HSI2C_CTL);<br>
+ i2c_ctl &= ~HSI2C_SW_RST;<br>
+ writel(i2c_ctl, i2c->regs + HSI2C_CTL);<br>
+<br>
+ /* Initialize the configure registers */<br>
+ exynos5_i2c_init(i2c);<br>
+}<br>
+<br>
+static void exynos5_i2c_master_run(struct exynos5_i2c *i2c)<br>
<div class="im">+{<br>
+ /* Start data transfer in Master mode */<br>
</div>+ u32 i2c_auto_conf = readl(i2c->regs + HSI2C_AUTO_CONF);<br>
+ i2c_auto_conf |= HSI2C_MASTER_RUN;<br>
<div class="im">+ writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);<br>
+}<br>
+<br>
+/**<br>
+ * exynos5_i2c_irq: top level IRQ servicing routine<br>
+*/<br>
</div><div class="im">+static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)<br>
+{<br>
+ struct exynos5_i2c *i2c = dev_id;<br>
+ unsigned char byte;<br>
+<br></div></blockquote><div><br></div><div style>Can other sorts of irqs happen? Errors?</div><div style> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<div class="im">
+ if (i2c->msg->flags & I2C_M_RD) {<br>
</div>+ while (!(readl(i2c->regs + HSI2C_FIFO_STATUS) &<br>
+ HSI2C_RX_FIFO_EMPTY)) {<br>
<div class="im">+ byte = (unsigned char)readl(i2c->regs + HSI2C_RX_DATA);<br>
</div>+ i2c->msg->buf[i2c->msg_ptr++] = byte;<br>
+ }<br>
+ } else {<br>
+ byte = i2c->msg->buf[i2c->msg_ptr++];<br>
<div class="im">+ writel(byte, i2c->regs + HSI2C_TX_DATA);<br>
+<br></div></blockquote><div><br></div><div style>Extra blank line. Here you only write one byte - is there a tx FIFO also, so we can avoid doing one interrupt per transmit byte?</div><div style> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<div class="im">
+ }<br>
</div>+<br>
+ if (i2c->msg_ptr >= i2c->msg->len)<br>
+ exynos5_i2c_stop(i2c);<br>
+<br>
<div class="im">+ /* Set these bits to clear them */<br>
+ writel(readl(i2c->regs + HSI2C_INT_STATUS),<br>
</div>+ i2c->regs + HSI2C_INT_STATUS);<br>
+<br>
<div class="im">+ return IRQ_HANDLED;<br></div></blockquote><div><br></div><div style>Are there any other interrupt types that can happen, like errors for example?</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<div class="im">
+}<br>
+<br>
</div>+static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)<br></blockquote><div><br></div><div style>Function comment would be useful - what is stop for?</div><div style> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
+{<br>
+ u32 i2c_ctl = readl(i2c->regs + HSI2C_CTL);<br>
+ u32 int_en = HSI2C_INT_I2C_EN;<br>
+ u32 i2c_auto_conf;<br>
+ u32 fifo_ctl;<br>
+<br>
+ exynos5_i2c_en_timeout(i2c);<br>
+<br>
+ fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN |<br>
+ HSI2C_TXFIFO_TRIGGER_LEVEL | HSI2C_RXFIFO_TRIGGER_LEVEL;<br>
+ writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);<br>
+<br></blockquote><div style><br></div><div style>You could</div><div style><br></div><div style> i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON)<br></div><div style><br></div><div style>here to simply code below.</div>
<div style> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<div class="im">+ if (i2c->msg->flags & I2C_M_RD) {<br>
</div>+ i2c_ctl &= ~HSI2C_TXCHON;<br>
+ i2c_ctl |= HSI2C_RXCHON;<br>
<div class="im">+<br>
+ i2c_auto_conf |= HSI2C_READ_WRITE;<br>
+<br>
</div>+ int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |<br>
+ HSI2C_INT_TRAILING_EN);<br>
+ } else {<br>
+ i2c_ctl &= ~HSI2C_RXCHON;<br>
+ i2c_ctl |= HSI2C_TXCHON;<br>
+<br>
+ int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;<br>
<div class="im">+ }<br>
+<br>
+ if (stop == 1)<br>
+ i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;<br>
+<br>
</div>+ writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR);<br>
+<br>
+ writel(i2c_ctl, i2c->regs + HSI2C_CTL);<br>
+<br>
+ /* In auto mode the length of xfer cannot be 0 */<br></blockquote><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
+ if (i2c->msg->len <= 0) </blockquote><div><br class="">What is auto mode? Perhaps a little comment at the top of the file about the two modes? What does it mean when msg->len < 0?</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
+ i2c_auto_conf |= 0x1;<br>
+ else<br>
<div class="im">+ i2c_auto_conf |= i2c->msg->len;<br>
+<br>
</div><div class="im">+ writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);<br>
+<br>
+ exynos5_i2c_master_run(i2c);<br>
+<br>
</div>+ writel(int_en, i2c->regs + HSI2C_INT_ENABLE);<br>
+}<br>
+<br>
<div class="im">+static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,<br>
</div>+ struct i2c_msg *msgs, int stop)<br>
<div class="im">+{<br>
+ unsigned long timeout;<br>
</div>+ u32 trans_status;<br>
+ u32 fifo_stat;<br>
+ int ret = -EAGAIN, val;<br>
<div class="im">+<br>
+ i2c->msg = msgs;<br>
</div><div class="im">+ i2c->msg_ptr = 0;<br>
+<br>
</div>+ exynos5_i2c_message_start(i2c, stop);<br>
+<br>
+ val = wait_for_completion_interruptible_timeout<br>
+ (&i2c->msg_complete, EXYNOS5_I2C_TIMEOUT);<br>
+ if (val >= 0)<br>
+ timeout = val;<br>
<div class="im">+<br>
+ if (msgs->flags & I2C_M_RD) {<br>
</div><div class="im">+ if (timeout == 0) {<br>
+ exynos5_i2c_reset(i2c);<br>
+ dev_warn(i2c->dev, "rx timeout\n");<br>
+ return ret;<br>
+ }<br>
+<br>
+ ret = 0;<br>
</div>+ } else {<br>
<div class="im">+ if (timeout == 0) {<br>
+ exynos5_i2c_reset(i2c);<br>
+ dev_warn(i2c->dev, "tx timeout\n");<br>
+ return ret;<br>
+ }<br></div></blockquote><div><br></div><div style>Could perhaps make the timeout check common (put above the if (msgs->flags)).</div><div style> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<div class="im">
+<br>
+ timeout = jiffies + timeout;<br>
+<br>
+ while (time_before(jiffies, timeout)) {<br>
</div>+ fifo_stat = readl(i2c->regs + HSI2C_FIFO_STATUS);<br>
<div class="im">+ trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);<br>
</div>+ if ((trans_status & HSI2C_NO_DEV) ||<br>
+ (trans_status & HSI2C_NO_DEV_ACK &&<br>
+ !(i2c->msg->flags & I2C_M_IGNORE_NAK))) {<br>
+ exynos5_i2c_reset(i2c);<br></blockquote><div><br></div><div style>I think these continuation lines should be indented a little more.</div><div style> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
+ return -ENXIO;<br>
+ }<br>
+ if ((fifo_stat == HSI2C_FIFO_EMPTY) &&<br>
<div class="im">+ ((trans_status == 0) ||<br>
+ ((stop == 0) &&<br>
</div>+ (trans_status == HSI2C_MASTER_BUSY)))) {<br>
<div class="im">+ ret = 0;<br>
+ break;<br>
+ }<br>
+ }<br></div></blockquote><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div class="im">+ if (ret == -EAGAIN) {<br>
+ exynos5_i2c_reset(i2c);<br>
</div>+ dev_warn(i2c->dev, "xfer timeout\n");<br>
<div class="im">+ return ret;<br>
+ }<br>
+ }<br>
+<br>
+ return ret;<br>
+}<br>
+<br>
+static int exynos5_i2c_xfer(struct i2c_adapter *adap,<br>
+ struct i2c_msg *msgs, int num)<br>
+{<br>
+ struct exynos5_i2c *i2c = (struct exynos5_i2c *)adap->algo_data;<br>
+ int retry, i;<br>
</div>+ int ret, ret_pm;<br>
<div class="im">+ int stop = 0;<br>
+ struct i2c_msg *msgs_ptr = msgs;<br>
+<br>
+ if (i2c->suspended) {<br>
+ dev_err(i2c->dev, "HS-I2C is not initialzed.\n");<br>
+ return -EIO;<br>
+ }<br>
+<br>
</div>+ ret_pm = pm_runtime_get_sync(i2c->dev);<br>
+ if (IS_ERR_VALUE(ret_pm)) {<br>
+ ret = -EIO;<br>
+ goto out;<br>
<div class="im">+ }<br>
+<br>
+ clk_prepare_enable(i2c->clk);<br>
+<br>
+ for (retry = 0; retry < adap->retries; retry++) {<br>
+ for (i = 0; i < num; i++) {<br>
+ if (i == num - 1)<br>
+ stop = 1;<br></div></blockquote><div><br></div><div style>Perhaps:</div><div style><br></div><div style>stop = (i == num - 1);</div><div style><br></div><div style>so you can avoid the other assignments to stop</div>
<div style> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div class="im">
</div>+ ret = exynos5_i2c_xfer_msg(i2c, msgs_ptr, stop);<br>
<div class="im">+ msgs_ptr++;<br>
+<br>
+ if (ret == -EAGAIN) {<br>
+ msgs_ptr = msgs;<br>
+ stop = 0;<br>
+ break;<br>
</div>+ } else if (ret == -ENXIO)<br>
+ goto out;<br></blockquote><div><br></div><div style>{} around else part also I think</div><div style> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<div class="im">+ }<br>
+ if (i == num) {<br>
</div><div class="im">+ ret = num;<br>
+ goto out;<br>
</div><div class="im">+ }<br>
+<br>
+ dev_dbg(i2c->dev, "retrying transfer (%d)\n", retry);<br>
+<br>
+ udelay(100);<br>
+ }<br>
+<br>
</div><div class="im">+ ret = -EREMOTEIO;<br></div></blockquote><div><br></div><div style>Perhaps a dev_warn() here?</div><div style> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<div class="im">
+ out:<br>
+ clk_disable_unprepare(i2c->clk);<br>
+ pm_runtime_mark_last_busy(i2c->dev);<br>
+ pm_runtime_put_autosuspend(i2c->dev);<br>
</div><div class="im">+ return ret;<br>
+}<br>
+<br>
</div><div class="im">+static u32 exynos5_i2c_func(struct i2c_adapter *adap)<br>
+{<br>
</div>+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;<br>
<div class="im">+}<br>
+<br>
+static const struct i2c_algorithm exynos5_i2c_algorithm = {<br>
+ .master_xfer = exynos5_i2c_xfer,<br>
+ .functionality = exynos5_i2c_func,<br>
+};<br>
+<br>
</div><div class="im">+/**<br>
+ * Parse a list of GPIOs from a node property and request each one<br>
+ *<br>
+ * @param i2c i2c driver data<br>
+ * @return 0 on success, -EINVAL on error, in which case no GPIOs requested<br>
+*/<br>
</div><div class="im">+static int exynos5_i2c_parse_dt_gpio(struct exynos5_i2c *i2c)<br>
+{<br>
+ int idx, gpio, ret;<br>
+<br>
+ for (idx = 0; idx < 2; idx++) {<br>
+ gpio = of_get_gpio(i2c->dev->of_node, idx);<br>
+ if (!gpio_is_valid(gpio)) {<br>
+ dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio);<br>
</div>+ return -EINVAL;<br>
<div class="im">+ }<br>
+ i2c->gpios[idx] = gpio;<br>
+<br>
</div>+ ret = devm_gpio_request(i2c->dev, gpio, "i2c-bus");<br>
<div class="im">+ if (ret) {<br>
+ dev_err(i2c->dev, "gpio [%d] request failed\n", gpio);<br>
</div>+ return -EINVAL;<br>
<div class="im">+ }<br>
+ }<br>
+ return 0;<br>
+}<br>
+<br>
</div><div class="im">+#define HSI2C_REG(regname) {.name = #regname, .offset = regname}<br>
+static struct debugfs_reg32 exynos5_hsi2c_regs[] = {<br>
+ HSI2C_REG(HSI2C_CTL), HSI2C_REG(HSI2C_FIFO_CTL),<br>
+ HSI2C_REG(HSI2C_TRAILIG_CTL), HSI2C_REG(HSI2C_CLK_CTL),<br>
+ HSI2C_REG(HSI2C_CLK_SLOT), HSI2C_REG(HSI2C_INT_ENABLE),<br>
+ HSI2C_REG(HSI2C_INT_STATUS), HSI2C_REG(HSI2C_ERR_STATUS),<br>
+ HSI2C_REG(HSI2C_FIFO_STATUS), HSI2C_REG(HSI2C_TX_DATA),<br>
+ HSI2C_REG(HSI2C_RX_DATA), HSI2C_REG(HSI2C_CONF),<br>
+ HSI2C_REG(HSI2C_AUTO_CONF), HSI2C_REG(HSI2C_TIMEOUT),<br>
+ HSI2C_REG(HSI2C_MANUAL_CMD), HSI2C_REG(HSI2C_TRANS_STATUS),<br>
+ HSI2C_REG(HSI2C_TIMING_HS1), HSI2C_REG(HSI2C_TIMING_HS2),<br>
+ HSI2C_REG(HSI2C_TIMING_HS3), HSI2C_REG(HSI2C_TIMING_FS1),<br>
+ HSI2C_REG(HSI2C_TIMING_FS2), HSI2C_REG(HSI2C_TIMING_FS3),<br>
+ HSI2C_REG(HSI2C_TIMING_SLA), HSI2C_REG(HSI2C_ADDR),<br>
+};<br>
+<br>
+static struct debugfs_regset32 exynos5_hsi2c_regset = {<br>
+ .regs = exynos5_hsi2c_regs,<br>
+ .nregs = ARRAY_SIZE(exynos5_hsi2c_regs),<br>
+};<br>
+<br>
+static struct dentry *exynos5_hsi2c_reg_debugfs;<br>
</div><div class="im">+<br>
+static int exynos5_i2c_probe(struct platform_device *pdev)<br>
+{<br>
</div><div class="im">+ struct device_node *np = pdev->dev.of_node;<br>
</div>+ struct exynos5_i2c *i2c;<br>
<div class="im">+ int ret;<br>
+<br>
+ if (!np) {<br>
</div><div class="im">+ dev_err(&pdev->dev, "no device node\n");<br>
+ return -ENOENT;<br>
+ }<br>
+<br>
</div><div class="im">+ i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);<br>
+ if (!i2c) {<br>
+ dev_err(&pdev->dev, "no memory for state\n");<br>
+ return -ENOMEM;<br>
+ }<br>
+<br>
</div><div class="im">+ /* Mode of operation High/Fast Speed mode */<br>
</div>+ if (of_get_property(np, "samsung,hs-mode", NULL)) {<br>
<div class="im">+ i2c->speed_mode = 1;<br>
</div><div class="im">+ if (of_property_read_u32(np, "samsung,hs-clock", &i2c->clock))<br>
+ i2c->clock = HSI2C_HS_TX_CLOCK;<br>
+ } else {<br>
</div>+ i2c->speed_mode = 0;<br>
<div class="im">+ if (of_property_read_u32(np, "samsung,fs-clock", &i2c->clock))<br>
+ i2c->clock = HSI2C_FS_TX_CLOCK;<br>
</div>+ }<br>
+<br>
+ strlcpy(i2c-><a href="http://adap.name" target="_blank">adap.name</a>, "exynos5-i2c", sizeof(i2c-><a href="http://adap.name" target="_blank">adap.name</a>));<br>
<div class="im">+ i2c->adap.owner = THIS_MODULE;<br>
+ i2c->adap.algo = &exynos5_i2c_algorithm;<br>
+ i2c->adap.retries = 2;<br>
+ i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;<br>
+<br>
+ i2c->dev = &pdev->dev;<br>
</div>+ i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");<br>
<div class="im">+ if (IS_ERR(i2c->clk)) {<br>
+ dev_err(&pdev->dev, "cannot get clock\n");<br>
</div><div class="im">+ return -ENOENT;<br>
+ }<br>
+<br>
</div>+ clk_prepare_enable(i2c->clk);<br>
+<br>
<div class="im">+ i2c->regs = of_iomap(np, 0);<br>
+ if (!i2c->regs) {<br>
</div><div class="im">+ dev_err(&pdev->dev, "cannot map HS-I2C IO\n");<br>
</div>+ ret = -EADDRNOTAVAIL;<br>
<div class="im">+ goto err_clk;<br>
+ }<br>
+<br>
</div><div class="im">+ i2c->adap.algo_data = i2c;<br>
+ i2c->adap.dev.parent = &pdev->dev;<br>
+<br>
</div><div class="im">+ /* parse device tree and inititalise the gpio */<br>
</div><div class="im">+ if (exynos5_i2c_parse_dt_gpio(i2c))<br>
+ return -EINVAL;<br>
+<br>
</div>+ init_completion(&i2c->msg_complete);<br>
+<br>
+ i2c->irq = ret = irq_of_parse_and_map(np, 0);<br>
<div class="im">+ if (ret <= 0) {<br>
+ dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");<br>
+ goto err_iomap;<br>
+ }<br>
+<br>
</div><div class="im">+ ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,<br>
</div>+ 0, dev_name(&pdev->dev), i2c);<br>
<div class="im">+<br>
+ if (ret != 0) {<br>
+ dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);<br>
+ goto err_iomap;<br>
+ }<br>
+<br>
</div><div class="im">+ /*<br>
+ * TODO: Use private lock to avoid race conditions as<br>
+ * mentioned in pm_runtime.txt<br>
+ */<br>
+ pm_runtime_enable(i2c->dev);<br>
+ pm_runtime_set_autosuspend_delay(i2c->dev, EXYNOS5_I2C_PM_TIMEOUT);<br>
+ pm_runtime_use_autosuspend(i2c->dev);<br>
+<br>
+ ret = pm_runtime_get_sync(i2c->dev);<br>
+ if (IS_ERR_VALUE(ret))<br>
</div>+ goto err_iomap;<br>
+<br>
+ exynos5_i2c_init(i2c);<br>
+ i2c-><a href="http://adap.nr" target="_blank">adap.nr</a> = -1;<br>
<div class="im">+ i2c->adap.dev.of_node = np;<br>
</div><div class="im">+<br>
+ ret = i2c_add_numbered_adapter(&i2c->adap);<br>
+ if (ret < 0) {<br>
+ dev_err(&pdev->dev, "failed to add bus to i2c core\n");<br>
</div>+ goto err_pm;<br>
<div class="im">+ }<br>
+<br>
+ of_i2c_register_devices(&i2c->adap);<br>
+ platform_set_drvdata(pdev, i2c);<br>
+<br>
</div><div class="im">+ exynos5_hsi2c_reg_debugfs = debugfs_create_regset32("exynos5-hsi2c",<br>
+ S_IFREG | S_IRUGO,<br>
+ NULL, &exynos5_hsi2c_regset);<br>
+ clk_disable_unprepare(i2c->clk);<br>
+ pm_runtime_mark_last_busy(i2c->dev);<br>
+ pm_runtime_put_autosuspend(i2c->dev);<br>
</div><div class="im">+<br>
+ return 0;<br>
+<br>
</div><div class="im">+ err_pm:<br>
+ pm_runtime_put(i2c->dev);<br>
+ pm_runtime_disable(&pdev->dev);<br>
</div><div class="im">+ err_iomap:<br>
+ iounmap(i2c->regs);<br>
</div><div class="im">+ err_clk:<br>
+ clk_disable_unprepare(i2c->clk);<br>
</div><div class="im">+ return ret;<br>
+}<br>
+<br>
+static int exynos5_i2c_remove(struct platform_device *pdev)<br>
+{<br>
+ struct exynos5_i2c *i2c = platform_get_drvdata(pdev);<br>
</div><div class="im">+ int ret;<br>
+<br>
+ ret = pm_runtime_get_sync(&pdev->dev);<br>
+ if (IS_ERR_VALUE(ret))<br>
</div>+ return ret;<br>
+<br>
<div class="im">+ clk_disable_unprepare(i2c->clk);<br>
+ pm_runtime_put(&pdev->dev);<br>
+ pm_runtime_disable(&pdev->dev);<br>
</div><div class="im">+<br>
+ i2c_del_adapter(&i2c->adap);<br>
+<br>
</div>+ iounmap(i2c->regs);<br>
+<br>
<div class="im">+ return 0;<br>
+}<br>
+<br>
+#ifdef CONFIG_PM<br>
+static int exynos5_i2c_suspend_noirq(struct device *dev)<br></div></blockquote><div><br></div><div style>Have you selected the noirq methods for a reason? I am just interested in how you decided to use suspend_noirq() instead of suspend().</div>
<div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div class="im">
+{<br>
+ struct platform_device *pdev = to_platform_device(dev);<br>
+ struct exynos5_i2c *i2c = platform_get_drvdata(pdev);<br>
+<br>
</div><div class="im">+ i2c->suspended = 1;<br>
+<br>
</div><div class="im">+ return 0;<br>
+}<br>
+<br>
</div>+static int exynos5_i2c_resume_noirq(struct device *dev)<br>
<div class="im">+{<br>
+ struct platform_device *pdev = to_platform_device(dev);<br>
+ struct exynos5_i2c *i2c = platform_get_drvdata(pdev);<br>
+<br>
</div><div class="im">+ clk_prepare_enable(i2c->clk);<br>
+ exynos5_i2c_init(i2c);<br>
+ clk_disable_unprepare(i2c->clk);<br>
+ i2c->suspended = 0;<br>
+<br>
</div><div class="im">+ return 0;<br>
+}<br>
+<br>
+static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {<br>
+ .suspend_noirq = exynos5_i2c_suspend_noirq,<br>
</div>+ .resume_noirq = exynos5_i2c_resume_noirq,<br>
<div class="im">+};<br>
+<br>
+#define EXYNOS5_DEV_PM_OPS (&exynos5_i2c_dev_pm_ops)<br>
+#else<br>
+#define EXYNOS5_DEV_PM_OPS NULL<br>
+#endif<br>
+<br>
+static struct platform_driver exynos5_i2c_driver = {<br>
+ .probe = exynos5_i2c_probe,<br>
+ .remove = exynos5_i2c_remove,<br>
</div><div class="im">+ .driver = {<br>
+ .owner = THIS_MODULE,<br>
</div>+ .name = "exynos5-hsi2c",<br>
<div class="im">+ .pm = EXYNOS5_DEV_PM_OPS,<br>
+ .of_match_table = of_match_ptr(exynos5_i2c_match),<br>
+ },<br>
+};<br>
+<br>
+static int __init i2c_adap_exynos5_init(void)<br>
+{<br>
+ return platform_driver_register(&exynos5_i2c_driver);<br>
+}<br>
+subsys_initcall(i2c_adap_exynos5_init);<br>
+<br>
+static void __exit i2c_adap_exynos5_exit(void)<br>
+{<br>
+ platform_driver_unregister(&exynos5_i2c_driver);<br>
+}<br>
+module_exit(i2c_adap_exynos5_exit);<br>
+<br>
+MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");<br>
</div>+MODULE_AUTHOR("Naveen Krishna Chatradhi, <<a href="mailto:ch.naveen@samsung.com">ch.naveen@samsung.com</a>>");<br>
<div class=""><div class="h5">+MODULE_AUTHOR("Taekgyun Ko, <<a href="mailto:taeggyun.ko@samsung.com">taeggyun.ko@samsung.com</a>>");<br>
+MODULE_LICENSE("GPL");<br>
</div></div><span class=""><font color="#888888">--<br>
1.7.9.5<br>
<br></font></span></blockquote><div><br></div><div style>Regards,</div><div style>Simon</div><div style> </div></div><br></div></div>